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    Managing Read Timing in Semiconductor Devices
    1.
    发明公开
    Managing Read Timing in Semiconductor Devices 审中-公开

    公开(公告)号：US20240311014A1

    公开(公告)日：2024-09-19

    申请号：US18524337

    申请日：2023-11-30

    Applicant: Macronix International Co., Ltd.

    Inventor： Wu-Chin Peng ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing read timing in semiconductor devices are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to read stored data from the memory array. The circuitry is configured to: obtain a starting address of target data to be read based on a read instruction, determine that the starting address is in a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective reading speed, and read out the target data from the memory array based on the starting address being in the first address group.

    MANAGING CONTENT ADDRESSABLE MEMORY DEVICES
    2.
    发明公开
    MANAGING CONTENT ADDRESSABLE MEMORY DEVICES 审中-公开

    公开(公告)号：US20240118806A1

    公开(公告)日：2024-04-11

    申请号：US17961176

    申请日：2022-10-06

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.

    Memory circuit
    4.
    发明授权
    Memory circuit 有权

    公开(公告)号：US10770119B2

    公开(公告)日：2020-09-08

    申请号：US16534992

    申请日：2019-08-07

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Ming-Chih Hsieh

    IPC: G11C5/14 ,  G11C7/10 ,  G11C7/06

    Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

    Devices and operation methods for configuring data strobe signal in memory device
    7.
    发明授权
    Devices and operation methods for configuring data strobe signal in memory device 有权

    公开(公告)号：US09652228B2

    公开(公告)日：2017-05-16

    申请号：US14677321

    申请日：2015-04-02

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chang-Ting Chen

    IPC: G06F12/00 ,  G06F9/00

    CPC classification number: G06F9/00 ,  G06F1/12 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C16/00 ,  G11C29/023

    Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.

    DECODE SWITCH AND METHOD FOR CONTROLLING DECODE SWITCH
    10.
    发明申请
    DECODE SWITCH AND METHOD FOR CONTROLLING DECODE SWITCH 有权
    解码开关和控制解码开关的方法

    公开(公告)号：US20160204697A1

    公开(公告)日：2016-07-14

    申请号：US14693565

    申请日：2015-04-22

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Yi-Fan Chang ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: H02M3/10 ,  H03K17/30

    CPC classification number: H03K17/007 ,  G11C8/00 ,  G11C8/10 ,  H03K2217/0036

    Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

    Abstract translation: 提供了解码开关和用于控制解码开关的方法。 解码开关包括提供第一电压的电源，耦合到电源的源电容和耦合到电源的目标电容。 电源将源电容充电到第一电压。 源电容连接到目标电容，源电容将目标电容充电到第二电压。 电源将目标电容从第二电压充电到第一电压。

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