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    Memory chip having security verification function and memory device
    1.
    发明授权
    Memory chip having security verification function and memory device 有权

    公开(公告)号：US11520933B2

    公开(公告)日：2022-12-06

    申请号：US16726284

    申请日：2019-12-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F21/72 ,  G06F21/62 ,  G06F12/1009

    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

    MEMORY CIRCUIT
    3.
    发明申请
    MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20200185010A1

    公开(公告)日：2020-06-11

    申请号：US16534992

    申请日：2019-08-07

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Ming-Chih Hsieh

    IPC: G11C5/14 ,  G11C7/10 ,  G11C7/06

    Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

    Method and system for a serial peripheral interface
    4.
    再颁专利
    Method and system for a serial peripheral interface 有权

    公开(公告)号：USRE47803E1

    公开(公告)日：2020-01-07

    申请号：US14995059

    申请日：2016-01-13

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

    IPC: G11C7/10 ,  G11C7/22

    Abstract: An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

    NESTED WRAP-AROUND MEMORY ACCESS
    7.
    发明申请
    NESTED WRAP-AROUND MEMORY ACCESS 审中-公开

    公开(公告)号：US20190073300A1

    公开(公告)日：2019-03-07

    申请号：US16180930

    申请日：2018-11-05

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F12/06

    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

    NON-VOLATILE MEMORY WITH SECURITY KEY STORAGE
    9.
    发明申请
    NON-VOLATILE MEMORY WITH SECURITY KEY STORAGE 审中-公开

    公开(公告)号：US20180039581A1

    公开(公告)日：2018-02-08

    申请号：US15601582

    申请日：2017-05-22

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang

    IPC: G06F12/14 ,  H04L9/08 ,  G06F13/42

    Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

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