Invention Grant
- Patent Title: Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices
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Application No.: US14725663Application Date: 2015-05-29
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Publication No.: US09318388B2Publication Date: 2016-04-19
- Inventor: Ruilong Xie , Vimal K. Kamineni , Abner F. Bello , Nicholas V. LiCausi , Wenhui Wang , Michael Wedlake , Jason R. Cantone
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L21/8238 ; H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L29/165 ; H01L29/66 ; H01L27/092 ; H01L27/12 ; H01L27/108 ; H01L21/02 ; H01L21/308 ; H01L21/3213 ; H01L21/762 ; H01L29/78

Abstract:
One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.
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