公开(公告)号：US10343253B2

公开(公告)日：2019-07-09

申请号：US14311761

申请日：2014-06-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Abner Bello ,  Michael Wedlake

IPC: B24B37/04 ,  B24B37/27 ,  B24B37/005

Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.

公开(公告)号：US20160190306A1

公开(公告)日：2016-06-30

申请号：US15063633

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785 ,  H01L2029/7858

Abstract: One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.

Abstract translation: 本文公开的一个说明性装置尤其包括半导体衬底，翅片结构，位于器件的沟道区域中的翅片结构的一部分周围的栅极结构，第二半导体材料的间隔开的部分位于 所述翅片结构和所述基板，其中所述第二半导体材料是与所述翅片不同的半导体材料，以及局部通道隔离材料，其横向位于所述第二半导体材料的所述间隔开的部分之间并且垂直于所述翅片结构的下方， 栅极结构，其中所述局部沟道隔离材料位于所述器件的沟道区域的至少一部分的下方。

公开(公告)号：US09318388B2

公开(公告)日：2016-04-19

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

公开(公告)号：US20150294912A1

公开(公告)日：2015-10-15

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

公开(公告)号：US09412740B2

公开(公告)日：2016-08-09

申请号：US14855881

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.

Abstract translation: 所公开的一个说明性装置尤其包括被隔离区隔开的第一和第二有源区，分别位于第一和第二有源区上方的第一和第二置换栅极结构以及位于隔离区上方的栅极配准结构 ，其中所述栅极配准结构包括位于所述隔离区域上方的绝缘材料层和抛光停止层，并且其中所述第一替换栅极结构的第一端表面邻接并接合所述栅极配准结构的第一侧表面， 第二替换栅极结构的端面邻接并接合栅极配准结构的第二侧表面。

公开(公告)号：US09165836B1

公开(公告)日：2015-10-20

申请号：US14242046

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L21/70 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process.

Abstract translation: 公开的一种方法包括在隔离区域之上形成栅极配准结构，其中栅极配准结构包括多层材料，其最上层是抛光停止层，形成第一和第二牺牲栅极 分别在第一和第二有源区域之上的结构，其中第一和第二牺牲栅极结构邻接并接合栅极对准结构的相对侧，并且执行至少一个第一化学机械抛光（CMP）工艺以移除栅极盖层，以便 从而在第一和第二牺牲栅极结构中的每一个中露出牺牲栅电极，其中栅极配准结构的最上层在至少一个第一CMP工艺期间用作抛光停止层。

公开(公告)号：US20150228511A1

公开(公告)日：2015-08-13

申请号：US14176545

申请日：2014-02-10

Applicant: Globalfoundries, Inc.

Inventor： Michael Wedlake

IPC: H01L21/67 ,  H01L21/306

CPC classification number: H01L21/30625 ,  B24B1/04 ,  B24B37/07

Abstract: Methods and a system for processing semiconductor substrates are provided. A method of processing a semiconductor substrate includes selecting a predetermined vibration profile that will achieve predetermined material removal characteristics from the semiconductor substrate in a chemical mechanical planarization (CMP) polish, actuating a vibration actuator based on the predetermined vibration profile, and polishing the semiconductor substrate based substantially entirely on the predetermined vibration profile achieved by actuation of the vibration actuator.

Abstract translation: 提供了用于处理半导体衬底的方法和系统。 一种处理半导体衬底的方法包括：在化学机械平面化（CMP）抛光中选择将从半导体衬底获得预定的材料去除特性的预定振动分布，基于预定的振动分布来致动振动致动器，以及研磨半导体衬底 基本上完全基于通过致动振动致动器实现的预定振动分布。

公开(公告)号：US20150129934A1

公开(公告)日：2015-05-14

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US20160005733A1

公开(公告)日：2016-01-07

申请号：US14855881

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.

Abstract translation: 所公开的一个说明性装置尤其包括被隔离区隔开的第一和第二有源区，分别位于第一和第二有源区上方的第一和第二置换栅极结构以及位于隔离区上方的栅极配准结构 ，其中所述栅极配准结构包括位于所述隔离区域上方的绝缘材料层和抛光停止层，并且其中所述第一替换栅极结构的第一端表面邻接并接合所述栅极配准结构的第一侧表面， 第二替换栅极结构的端面邻接并接合栅极配准结构的第二侧表面。

公开(公告)号：US20150371912A1

公开(公告)日：2015-12-24

申请号：US14311761

申请日：2014-06-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Abner Bello ,  Michael Wedlake

IPC: H01L21/66 ,  H01L21/67 ,  B24B37/04 ,  H01L21/306 ,  B24B37/005 ,  B24B37/27

CPC classification number: B24B37/04 ,  B24B37/005 ,  B24B37/27

Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.

Abstract translation: 提供了用于检测半导体衬底上的化学机械平面化（CMP）工艺的端点的方法，非暂时计算机可读介质和系统。 该方法包括生成参考信号，产生用于控制CMP系统的第一信号，使用第一信号和参考信号的组合产生第二信号，向CMP系统指示第二信号，产生响应信号，该响应信号 表示响应于第二信号和半导体衬底的摩擦特性的CMP系统的操作特性，并且使用参考信号对响应信号进行滤波以确定CMP过程的终点。