公开(公告)号：US20150129934A1

公开(公告)日：2015-05-14

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US09093302B2

公开(公告)日：2015-07-28

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US08975094B2

公开(公告)日：2015-03-10

申请号：US13745929

申请日：2013-01-21

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Abner F. Bello ,  Shubhankar Basu

IPC: H01L21/66 ,  G01R31/26 ,  G03F7/20

CPC classification number: H01L22/30 ,  G03F7/70483 ,  H01L22/12

Abstract: A test structure and method are provided to facilitate developing or optimizing a fabrication process by determining values of one or more lithography process parameters for use in semiconductor device fabrication. The test structure is configured to facilitate determining values of the one or more fabrication process parameters, and includes a plurality of test structure components arranged on a substrate according to a test pattern. The test pattern may be based on: varying distances between the test structure components according to a first rule; varying distances between centers of the test structure components according to a second rule; and/or varying at least one dimension of the test structure components according to a third rule. The method may further include determining dimensions of one or more components of the test structure using, for example, scatterometry, and using the dimensions of the components to ascertain one or more fabrication process parameters.

Abstract translation: 提供了一种测试结构和方法，以通过确定用于半导体器件制造的一个或多个光刻工艺参数的值来促进制造工艺的开发或优化。 测试结构被配置为便于确定一个或多个制造工艺参数的值，并且包括根据测试图案布置在基板上的多个测试结构组件。 测试模式可以基于：根据第一规则在测试结构组件之间改变距离; 根据第二规则，测试结构部件的中心之间的距离变化; 和/或根据第三规则改变测试结构部件的至少一个维度。 该方法还可以包括使用例如散射法确定测试结构的一个或多个部件的尺寸，并且使用部件的尺寸来确定一个或多个制造工艺参数。

公开(公告)号：US20160190306A1

公开(公告)日：2016-06-30

申请号：US15063633

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785 ,  H01L2029/7858

Abstract: One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.

Abstract translation: 本文公开的一个说明性装置尤其包括半导体衬底，翅片结构，位于器件的沟道区域中的翅片结构的一部分周围的栅极结构，第二半导体材料的间隔开的部分位于 所述翅片结构和所述基板，其中所述第二半导体材料是与所述翅片不同的半导体材料，以及局部通道隔离材料，其横向位于所述第二半导体材料的所述间隔开的部分之间并且垂直于所述翅片结构的下方， 栅极结构，其中所述局部沟道隔离材料位于所述器件的沟道区域的至少一部分的下方。

公开(公告)号：US09318388B2

公开(公告)日：2016-04-19

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

公开(公告)号：US20150294912A1

公开(公告)日：2015-10-15

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

公开(公告)号：US20140203279A1

公开(公告)日：2014-07-24

申请号：US13745929

申请日：2013-01-21

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Abner F. Bello ,  Shubhankar Basu

IPC: H01L21/66

CPC classification number: H01L22/30 ,  G03F7/70483 ,  H01L22/12

Abstract: A test structure and method are provided to facilitate developing or optimizing a fabrication process by determining values of one or more lithography process parameters for use in semiconductor device fabrication. The test structure is configured to facilitate determining values of the one or more fabrication process parameters, and includes a plurality of test structure components arranged on a substrate according to a test pattern. The test pattern may be based on: varying distances between the test structure components according to a first rule; varying distances between centers of the test structure components according to a second rule; and/or varying at least one dimension of the test structure components according to a third rule. The method may further include determining dimensions of one or more components of the test structure using, for example, scatterometry, and using the dimensions of the components to ascertain one or more fabrication process parameters.

Abstract translation: 提供了一种测试结构和方法，以通过确定用于半导体器件制造的一个或多个光刻工艺参数的值来促进制造工艺的开发或优化。 测试结构被配置为便于确定一个或多个制造工艺参数的值，并且包括根据测试图案布置在基板上的多个测试结构组件。 测试模式可以基于：根据第一规则在测试结构组件之间改变距离; 根据第二规则，测试结构部件的中心之间的距离变化; 和/或根据第三规则改变测试结构部件的至少一个维度。 该方法还可以包括使用例如散射法确定测试结构的一个或多个部件的尺寸，并且使用部件的尺寸来确定一个或多个制造工艺参数。