Invention Grant
- Patent Title: Removing deterministic phase errors from fractional-N PLLs
- Patent Title (中): 从分数N个PLL中消除确定性相位误差
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Application No.: US14920440Application Date: 2015-10-22
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Publication No.: US09337852B2Publication Date: 2016-05-10
- Inventor: Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Bodhisatwa Sadhu , Alberto Valdes Garcia
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/197 ; H03L7/081 ; H03L7/085 ; H03L7/099

Abstract:
Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio.
Public/Granted literature
- US20160094232A1 REMOVING DETERMINISTIC PHASE ERRORS FROM FRACTIONAL-N PLLS Public/Granted day:2016-03-31
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