Invention Grant
US09343374B1 Efficient main spacer pull back process for advanced VLSI CMOS technologies
有权
先进的VLSI CMOS技术的高效主间隔回拉工艺
- Patent Title: Efficient main spacer pull back process for advanced VLSI CMOS technologies
- Patent Title (中): 先进的VLSI CMOS技术的高效主间隔回拉工艺
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Application No.: US14527207Application Date: 2014-10-29
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Publication No.: US09343374B1Publication Date: 2016-05-17
- Inventor: Jan Hoentschel , Peter Javorka , Stefan Flachowsky , Ralf Richter
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/3205 ; H01L21/4763 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119 ; H01L21/8238 ; H01L29/66 ; H01L27/092 ; H01L29/78 ; H01L29/49

Abstract:
Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap.
Public/Granted literature
- US20160126146A1 EFFICIENT MAIN SPACER PULL BACK PROCESS FOR ADVANCED VLSI CMOS TECHNOLOGIES Public/Granted day:2016-05-05
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