公开(公告)号：US09876111B2

公开(公告)日：2018-01-23

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

公开(公告)号：US20170170317A1

公开(公告)日：2017-06-15

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

公开(公告)号：US09484459B2

公开(公告)日：2016-11-01

申请号：US14944833

申请日：2015-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

IPC: H01L27/10 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834

Abstract: A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material.

Abstract translation: 半导体器件包括位于晶体管的有源区域中的漏极和源极区域以及横向设置在漏极和源极区域之间的沟道区域，该沟道区域包括位于半导体基底材料上的半导体基底材料和阈值电压调节半导体材料。 门极电极结构位于阈值电压调节用半导体材料上，并且包含位于第一半导体材料上方的第一半导体材料和第二半导体材料的应变诱发半导体合金嵌入有源区的半导体基底材料中。 第三半导体材料的结晶缓冲层包围嵌入式应变诱导半导体合金，其中结晶缓冲层的上部横向限制包括阈值电压调节半导体材料的侧壁的沟道区，并且位于第二半导体材料 和阈值电压调节半导体材料。

公开(公告)号：US20160268426A1

公开(公告)日：2016-09-15

申请号：US15161399

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Abstract translation: 半导体器件包括多个间隔开的翅片，位于多个间隔开的翅片中的每一个之间的介电材料层，以及位于电介质材料层上方并延伸穿过翅片的公共栅极结构。 连续合并的半导体材料区域位于每个散热片上并且位于电介质材料层上方，与公共栅极结构横向间隔开，在翅片之间延伸并物理接触翅片，具有面向公共栅极结构的第一侧壁表面 并且具有与第一侧壁表面相对并且远离公共栅极结构的第二侧壁表面。 应力诱导材料定位在由至少第一侧壁表面，相邻的一对翅片的相对侧壁表面和介电材料层的上表面限定的空间中。

公开(公告)号：US09412848B1

公开(公告)日：2016-08-09

申请号：US14615529

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66772 ,  H01L29/78696

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract translation: 本公开提供了形成半导体器件和半导体器件的方法。 提供具有半导体层，掩埋绝缘材料层和体基板的SOI衬底部分，其中埋入绝缘材料层插入在半导体层和块状衬底之间。 SOI衬底部分随后被图案化以便在本体衬底上形成图案化的双层堆叠，该双层堆叠包括图案化的半导体层和图案化的掩埋绝缘材料层。 双层堆叠进一步被另外的绝缘材料层封闭，并且在另外的绝缘材料层上和周围形成电极材料。 这里，栅电极由体基板和电极材料形成，使得栅电极基本上围绕由图案化的掩埋绝缘材料层的一部分形成的沟道部分。

公开(公告)号：US20160204217A1

公开(公告)日：2016-07-14

申请号：US15076895

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/161 ,  H01L29/78 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor product with certain devices having a first device with a fully silicided (FuSi) gate and a second device with a partially silicided gate is disclosed. In one example, the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed above a layer of polysilicon or amorphous silicon during the silicidation process.

Abstract translation: 具有某些器件的半导体产品具有具有完全硅化（FuSi）栅极的第一器件和具有部分硅化栅极的第二器件。 在一个示例中，第一半导体器件凹入，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅电极材料上，在硅化处理期间，在多晶硅层或非晶硅层之上形成硅化物部分。

公开(公告)号：US09391176B2

公开(公告)日：2016-07-12

申请号：US14522000

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L25/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/165 ,  H01L25/065 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66818 ,  H01L25/0657 ,  H01L29/0634 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract translation: 本公开在本公开的各个方面提供一种半导体器件，其包括设置在衬底的表面上的半导体堆叠和部分地形成在半导体堆叠的上表面和两个相对的侧壁表面上的栅极结构，其中， 半导体堆叠包括由第一半导体材料和与第一半导体材料不同的第二半导体材料形成的至少两层的交替布置。

公开(公告)号：US09054044B2

公开(公告)日：2015-06-09

申请号：US13788719

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3083 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract translation: 提供了用于形成半导体器件的半导体器件结构和方法。 在实施例中，提供一个或多个翅片，所述一个或多个翅片中的每一个具有设置在下部的下部和上部。 下部嵌入第一绝缘材料中。 上部的形状是基本上三角形形状和大致圆形形状和大致梯形形状中的至少一个。 此外，在上部形成有与第一绝缘材料不同的第二绝缘材料层。

公开(公告)号：US20140273375A1

公开(公告)日：2014-09-18

申请号：US13842077

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Peter Javorka ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/266 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一牺牲氧化物层被形成在半导体衬底上，并且第一注入掩模被图案化成覆盖在第一牺牲氧化物层上以暴露与栅电极结构相邻的第一牺牲氧化物层的一部分。 电导率确定离子通过第一牺牲氧化物层注入到半导体衬底中。 在将导电性确定离子注入半导体衬底之后，去除第一注入掩模和第一牺牲氧化物层。

公开(公告)号：US08759922B2

公开(公告)日：2014-06-24

申请号：US13959237

申请日：2013-08-05

Applicant: GlobalFoundries Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Thilo Scheiper

IPC: H01L29/78 ,  H01L27/01 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66507 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7845

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract translation: 半导体器件形成为没有栅极的完全硅化，并且独立调节栅极和源极/漏极区域中的硅化物。 实施例包括在基板上形成栅极，在栅极上形成氮化物盖，在栅极的每一侧形成源/漏区，在每个源/漏区中形成第一硅化物，在形成 第一硅化物，并且在去除氮化物盖之后，在源极/漏极区域和栅极中形成第二硅化物。 实施例包括通过在源极/漏极区上形成第一金属层并执行第一RTA来形成第一硅化物，以及通过在源极/漏极区域和栅极上形成第二金属层并执行第二RTA形成第二硅化物 。