Invention Grant
US09343399B2 Thick conductive stack plating process with fine critical dimension feature size for compact passive on glass technology
有权
厚导电叠层电镀工艺，具有精细的临界尺寸特征尺寸，适用于紧凑的被动玻璃技术
- Patent Title: Thick conductive stack plating process with fine critical dimension feature size for compact passive on glass technology
- Patent Title (中): 厚导电叠层电镀工艺，具有精细的临界尺寸特征尺寸，适用于紧凑的被动玻璃技术
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Application No.: US14149530Application Date: 2014-01-07
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Publication No.: US09343399B2Publication Date: 2016-05-17
- Inventor: Je-Hsiung Lan , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim , Daeik Daniel Kim , Mario Francisco Velez , Robert Paul Mikulka , Niranjan Sunil Mudakatte
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Seyfarth Shaw LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L23/498 ; H01L23/522 ; H01L23/64 ; H01L27/01 ; H01L27/08 ; H01L49/02
Abstract:
An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.
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Information query
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