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公开(公告)号：US09449753B2
公开(公告)日：2016-09-20
申请号：US14155244
申请日：2014-01-14
发明人： Daeik Daniel Kim , Chengjie Zuo , Changhan Hobie Yun , Mario Francisco Velez , Robert Paul Mikulka , Xiangdong Zhang , Jonghae Kim , Je-Hsiung Lan
CPC分类号： H01F41/041 , H01F17/0013 , H01F27/2804 , H01F41/042 , H01F2017/0053 , H01F2017/0073 , H01F2027/2809
摘要： A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.
摘要翻译： 特定器件包括衬底和耦合到衬底的螺旋电感器。 螺旋电感器包括覆盖第一导电螺旋的第一导电螺旋和第二导电螺旋。 螺旋电感器的最内圈的第一部分在垂直于衬底的方向上具有第一厚度。 最内圈的第一部分包括第一导电螺旋的第一部分，并且不包括第二导电螺旋。 最内圈的第二部分包括第二导电螺旋的第一部分。 螺旋电感器的最外圈的一部分在垂直于衬底的方向上具有大于第一厚度的第二厚度。 最外圈的一部分包括第一导电螺旋的第二部分和第二导电螺旋的第二部分。
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公开(公告)号：US09343403B2
公开(公告)日：2016-05-17
申请号：US14483944
申请日：2014-09-11
发明人： Je-Hsiung Jeffrey Lan , David Francis Berdy , Chengjie Zuo , Daeik Daniel Kim , Changhan Hobie Yun , Mario Francisco Velez , Niranjan Sunil Mudakatte , Robert Paul Mikulka , Jonghae Kim
IPC分类号： H01L23/522 , H01L21/283 , H01L21/768 , H01L23/528 , H01L23/532 , H01L49/02
CPC分类号： H01L23/5227 , H01L21/283 , H01L21/76877 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/5329 , H01L27/01 , H01L28/10 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.
摘要翻译： 集成电路器件包括衬底。 集成电路器件还包括第一导电叠层，其包括参考衬底的第一高度处的后端行（BEOL）导电层。 集成电路器件还包括第二导电叠层，其包括相对于衬底的第二高度处的BEOL导电层。 第二个高程与第一个高程不同。
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公开(公告)号：US09275786B2
公开(公告)日：2016-03-01
申请号：US14335609
申请日：2014-07-18
发明人： David Francis Berdy , Chengjie Zuo , Daeik Daniel Kim , Changhan Hobie Yun , Mario Francisco Velez , Robert Paul Mikulka , Jonghae Kim
CPC分类号： H01F41/041 , H01F17/0013 , H01F27/2804 , H01F27/29 , H01F2017/004 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
摘要翻译： 三维（3D）正交电感器对被嵌入并由衬底支撑，并且具有第一电感器，其具有卷绕第一绕组轴线的第一线圈和具有卷绕第二绕组轴线的第二线圈的第二电感器 。 第二卷绕轴线与第一卷绕轴线正交。 第二绕组轴线在第一绕组轴线处于衬底内的交点处。
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4.发明申请DIE PACKAGE COMPRISING DIE-TO-WIRE CONNECTOR AND A WIRE-TO-DIE CONNECTOR CONFIGURED TO COUPLE TO A DIE PACKAGE 有权包含DIE至线连接器的DIE封装和配置为与DIE封装耦合的电线对连接器公开(公告)号：US20150303148A1
公开(公告)日：2015-10-22
申请号：US14254764
申请日：2014-04-16
发明人： Daeik Daniel Kim , Mario Francisco Velez , Jonghae Kim , Matthew Michael Nowak , Chengjie Zuo , Changhan Hobie Yun , David Francis Berdy , Robert Paul Mikulka
IPC分类号： H01L23/552 , H01L23/00 , H05K9/00 , H01L23/04 , H01L23/538 , H01L23/31 , H01L23/498
CPC分类号： H01L23/552 , H01L23/04 , H01L23/3107 , H01L23/32 , H01L23/49805 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5386 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/131 , H01L2224/13147 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01R12/7076 , H01R12/714 , H05K1/181 , H05K9/0032 , H05K2201/10189 , H05K2201/1053 , H05K2201/10734 , Y02P70/611 , H01L2924/014 , H01L2924/00014
摘要： Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.
摘要翻译： 一些新颖特征涉及包括封装衬底，管芯，封装层和第一组金属层的集成器件封装（例如管芯封装）。 封装衬底包括第一表面和第二表面。 管芯耦合到封装衬底的第一表面。 封装层封装模具。 第一组金属层耦合到封装层的第一外表面。 在一些实施方案中，第一组金属层被配置为作为集成器件封装的管芯到线连接器工作。 在一些实施方案中，集成器件封装包括耦合到封装衬底的第二表面的第二组金属层。 在一些实施方案中，集成器件封装包括耦合到封装层的第二外表面的第二组金属层。
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公开(公告)号：US09660110B2
公开(公告)日：2017-05-23
申请号：US14498359
申请日：2014-09-26
发明人： Daeik Daniel Kim , Jonghae Kim , Chengjie Zuo , Sang-June Park , Changhan Hobie Yun , Mario Francisco Velez , David Francis Berdy , Matthew Michael Nowak , Robert Paul Mikulka
CPC分类号： H01L29/93 , H01L27/0629 , H01L29/94
摘要： An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.
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公开(公告)号：US20170141756A1
公开(公告)日：2017-05-18
申请号：US15137662
申请日：2016-04-25
发明人： Changhan Hobie Yun , Chengjie Zuo , Daeik Daniel Kim , Mario Francisco Velez , Niranjan Sunil Mudakatte , Je-Hsiung Jeffrey Lan , David Francis Berdy , Yunfei Ma , Robert Paul Mikulka , Jonghae Kim
CPC分类号： H03H9/542 , H01F17/0013 , H01F2017/002 , H01F2017/0026 , H03H3/02 , H03H3/08 , H03H7/0123 , H03H7/461 , H03H9/0547 , H03H9/0557 , H03H9/0561 , H03H9/1014 , H03H9/1071 , H03H9/64 , H05K1/0306 , H05K1/185 , H05K3/0014 , H05K3/4602
摘要： A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.
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7.发明申请METAL-INSULATOR-METAL (MIM) CAPACITORS ARRANGED IN A PATTERN TO REDUCE INDUCTANCE, AND RELATED METHODS 审中-公开金属绝缘体金属（MIM）电容器，以减少电感的形态和相关方法公开(公告)号：US20160181233A1
公开(公告)日：2016-06-23
申请号：US14580900
申请日：2014-12-23
发明人： Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , Daeik Daniel Kim , David Francis Berdy , Chengjie Zuo , Jonghae Kim , Niranjan Sunil Mudakatte , Mario Francisco Velez , Robert Paul Mikulka
CPC分类号： H01L28/40 , H01G4/33 , H01G4/38 , H01L27/016 , H01L27/0805 , H01L2224/18
摘要： Metal-insulator-metal (MIM) capacitors arranged in a pattern to reduce inductance, and related methods, are disclosed. In one aspect, circuits are provided that employ MIM capacitors coupled in series. The MIM capacitors are arranged in a pattern, wherein a MIM capacitor is placed so as to be electromagnetically adjacent to at least two MIM capacitors, and so that a current of the MIM capacitor flows in a direction opposite or substantially opposite of a direction in which a current of each adjacent MIM capacitor flows. The magnetic field generated at metal connections of each MIM capacitor rotates in an opposite direction of the magnetic field of each electromagnetically adjacent MIM capacitor, and thus a larger proportion of magnetic fields cancel out one another rather than combining, reducing equivalent series inductance (ESL) compared to linear arrangement of MIMs.
摘要翻译： 公开了以图案排列以降低电感的金属绝缘体金属（MIM）电容器及相关方法。 在一个方面，提供了采用串联耦合的MIM电容器的电路。 MIM电容器以图案布置，其中MIM电容器放置成与至少两个MIM电容器电磁相邻，并且使得MIM电容器的电流沿与其中的MIM方向相反或基本上相反的方向流动 每个相邻MIM电容器的电流流动。 在每个MIM电容器的金属连接处产生的磁场沿与每个电磁相邻的MIM电容器的磁场相反的方向旋转，因此较大比例的磁场彼此抵消而不是组合，从而减小了等效串联电感（ESL） 与MIM的线性排列相比。
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公开(公告)号：US20150061813A1
公开(公告)日：2015-03-05
申请号：US14155244
申请日：2014-01-14
发明人： Daeik Daniel Kim , Chengjie Zuo , Changhan Hobie Yun , Mario Francisco Velez , Robert Paul Mikulka , Xiangdong Zhang , Jonghae Kim , Je-Hsiung Lan
CPC分类号： H01F41/041 , H01F17/0013 , H01F27/2804 , H01F41/042 , H01F2017/0053 , H01F2017/0073 , H01F2027/2809
摘要： A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.
摘要翻译： 特定器件包括衬底和耦合到衬底的螺旋电感器。 螺旋电感器包括覆盖第一导电螺旋的第一导电螺旋和第二导电螺旋。 螺旋电感器的最内圈的第一部分在垂直于衬底的方向上具有第一厚度。 最内圈的第一部分包括第一导电螺旋的第一部分，并且不包括第二导电螺旋。 最内圈的第二部分包括第二导电螺旋的第一部分。 螺旋电感器的最外圈的一部分在垂直于衬底的方向上具有大于第一厚度的第二厚度。 最外圈的一部分包括第一导电螺旋的第二部分和第二导电螺旋的第二部分。
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公开(公告)号：US10187031B2
公开(公告)日：2019-01-22
申请号：US15151351
申请日：2016-05-10
发明人： Yunfei Ma , Chengjie Zuo , David Francis Berdy , Daeik Daniel Kim , Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Niranjan Sunil Mudakatte , Robert Paul Mikulka , Jonghae Kim
摘要： A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.
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公开(公告)号：US10074625B2
公开(公告)日：2018-09-11
申请号：US14859323
申请日：2015-09-20
发明人： Mario Francisco Velez , David Francis Berdy , Changhan Hobie Yun , Jonghae Kim , Chengjie Zuo , Daeik Daniel Kim , Je-Hsiung Jeffrey Lan , Niranjan Sunil Mudakatte , Robert Paul Mikulka
IPC分类号： H01L23/00 , H01L23/13 , H01L23/498
CPC分类号： H01L24/17 , H01L23/13 , H01L23/49816 , H01L24/03 , H01L24/09 , H01L24/11 , H01L2224/023 , H01L2224/0905
摘要： An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.
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