Invention Grant
- Patent Title: Pillar bumps and process for making same
- Patent Title (中): 支柱颠簸和制作过程
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Application No.: US14468236Application Date: 2014-08-25
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Publication No.: US09449931B2Publication Date: 2016-09-20
- Inventor: Cheng-Chung Lin , Chung-Shi Liu , Meng-Wei Chou , Kuo Cheng Lin , Wen-Hsiung Lu , Chien Ling Hwang , Ying-Jui Huang , De-Yuan Lu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/4763 ; H01L23/00 ; H01L23/488 ; H01L21/321 ; H01L21/02 ; H01L21/768
Abstract:
Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.
Public/Granted literature
- US20140363966A1 Pillar Bumps and Process for Making Same Public/Granted day:2014-12-11
Information query
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