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公开(公告)号：US20180350629A1
公开(公告)日：2018-12-06
申请号：US16051303
申请日：2018-07-31
发明人： Zi-Jheng Liu , Yu-Hsiang Hu , Jo-Lin Lan , Sih-Hao Liao , Chen-Cheng Kuo , Hung-Jui Kuo , Chung-Shi Liu , Chen-Hua Yu , Meng-Wei Chou
CPC分类号： H01L21/561 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
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公开(公告)号：US12074104B2
公开(公告)日：2024-08-27
申请号：US18064417
申请日：2022-12-12
发明人： Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC分类号： H01L23/522 , H01L21/56 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/498
CPC分类号： H01L23/5226 , H01L21/56 , H01L21/563 , H01L21/76871 , H01L21/76877 , H01L23/3121 , H01L23/49827 , H01L24/09 , H01L24/14 , H01L2224/02372 , H01L2224/0401
摘要： In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.
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公开(公告)号：US20200006214A1
公开(公告)日：2020-01-02
申请号：US16118538
申请日：2018-08-31
发明人： Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48
摘要： A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
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公开(公告)号：US20170110421A1
公开(公告)日：2017-04-20
申请号：US15170487
申请日：2016-06-01
发明人： Zi-Jheng Liu , Yu-Hsiang Hu , Jo-Lin Lan , Sih-Hao Liao , Chen-Cheng Kuo , Hung-Jui Kuo , Chung-Shi Liu , Chen-Hua Yu , Meng-Wei Chou
CPC分类号： H01L21/561 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
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公开(公告)号：US09449931B2
公开(公告)日：2016-09-20
申请号：US14468236
申请日：2014-08-25
发明人： Cheng-Chung Lin , Chung-Shi Liu , Meng-Wei Chou , Kuo Cheng Lin , Wen-Hsiung Lu , Chien Ling Hwang , Ying-Jui Huang , De-Yuan Lu
IPC分类号： H01L21/44 , H01L21/4763 , H01L23/00 , H01L23/488 , H01L21/321 , H01L21/02 , H01L21/768
CPC分类号： H01L24/11 , H01L21/02052 , H01L21/32125 , H01L21/76873 , H01L21/76885 , H01L23/488 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2221/1084 , H01L2224/03912 , H01L2224/0401 , H01L2224/05073 , H01L2224/05541 , H01L2224/05573 , H01L2224/1111 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/11474 , H01L2224/11614 , H01L2224/1181 , H01L2224/11849 , H01L2224/11903 , H01L2224/1191 , H01L2224/11912 , H01L2224/13005 , H01L2224/13017 , H01L2224/13018 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/81191 , H01L2924/00013 , H01L2924/01006 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01059 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0541 , H01L2924/07025 , H01L2924/10329 , H01L2924/14 , H01L2924/20102 , H01L2924/3512 , H01L2924/381 , H01L2924/3841 , H01L2924/0105 , H01L2924/00014 , H01L2224/13099 , H01L2924/207
摘要： Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.
摘要翻译： 用于提供焊料柱凸块的装置和方法。 通过在集成电路的端子上形成导电材料的电镀，形成导电材料的柱，形成用于集成电路的输入/输出端子上的柱凸起连接。 柱状凸块的基部具有比上部更大的宽度。 柱形凸起的基部的横截面可以形成梯形，矩形或倾斜的形状。 焊料可以形成在柱的顶表面上。 所得到的焊料柱凸起形成比现有技术更可靠的细间距封装焊接连接。
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公开(公告)号：US11527474B2
公开(公告)日：2022-12-13
申请号：US17034805
申请日：2020-09-28
发明人： Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC分类号： H01L23/522 , H01L23/31 , H01L23/498 , H01L21/56 , H01L23/00 , H01L21/768
摘要： In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.
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公开(公告)号：US10790162B2
公开(公告)日：2020-09-29
申请号：US16207850
申请日：2018-12-03
发明人： Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC分类号： H01L21/56 , H01L23/522 , H01L23/498 , H01L23/31 , H01L23/00 , H01L21/768
摘要： In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.
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公开(公告)号：US10804254B2
公开(公告)日：2020-10-13
申请号：US16193358
申请日：2018-11-16
发明人： Po-Hao Tsai , Techi Wong , Po-Yao Chuang , Shin-Puu Jeng , Meng-Wei Chou , Meng-Liang Lin
摘要： Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
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公开(公告)号：US10304700B2
公开(公告)日：2019-05-28
申请号：US15170487
申请日：2016-06-01
发明人： Zi-Jheng Liu , Yu-Hsiang Hu , Jo-Lin Lan , Shih-Hao Liao , Chen-Cheng Kuo , Hung-Jui Kuo , Chung-Shi Liu , Chen-Hua Yu , Meng-Wei Chou
摘要： A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
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公开(公告)号：US11075151B2
公开(公告)日：2021-07-27
申请号：US16118538
申请日：2018-08-31
发明人： Po-Hao Tsai , Techi Wong , Meng-Wei Chou , Meng-Liang Lin , Po-Yao Chuang , Shin-Puu Jeng
IPC分类号： H01L21/50 , H01L23/498 , H01L23/00 , H01L21/48
摘要： A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
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