公开(公告)号：US20240282720A1

公开(公告)日：2024-08-22

申请号：US18651321

申请日：2024-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Shi Liu ,  Jiun Yi Wu ,  Chien-Hsun Lee

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/351 ,  H01L2924/3841

摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 μm to 30 μm; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.

公开(公告)号：US12002768B2

公开(公告)日：2024-06-04

申请号：US17458607

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chih Huang ,  Chih-Hao Chang ,  Po-Chun Lin ,  Chun-Ti Lu ,  Zheng-Gang Tsai ,  Shih-Wei Chen ,  Chia-Hung Liu ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC分类号： H01L23/58 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/585 ,  H01L21/568 ,  H01L23/3157 ,  H01L24/19 ,  H01L24/25 ,  H01L2224/2518

摘要： A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern. The conductive vias extend through the molded semiconductor device and are electrically connected with the redistribution pattern.

公开(公告)号：US11961814B2

公开(公告)日：2024-04-16

申请号：US17649430

申请日：2022-01-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hsun Chen ,  Shou-Yi Wang ,  Jiun Yi Wu ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L25/18

CPC分类号： H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/19 ,  H01L24/81 ,  H01L25/18 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/6627 ,  H01L2224/24137 ,  H01L2224/24225 ,  H01L2924/1431 ,  H01L2924/1434

摘要： In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.

公开(公告)号：US11837575B2

公开(公告)日：2023-12-05

申请号：US16806026

申请日：2020-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Kuo Lung Pan ,  Shu-Rong Chun ,  Chi-Hui Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC分类号： H01L23/64 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/367

CPC分类号： H01L24/94 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3672 ,  H01L23/49861 ,  H01L23/64 ,  H01L25/0655 ,  H01L25/50

摘要： A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

公开(公告)号：US11749535B2

公开(公告)日：2023-09-05

申请号：US16046211

申请日：2018-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Wei-Hung Lin ,  Kuei-Wei Huang ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00

CPC分类号： H01L21/563 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/06181 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13172 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/8123 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13166 ,  H01L2924/00014 ,  H01L2224/13172 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/11

摘要： A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

公开(公告)号：US11742254B2

公开(公告)日：2023-08-29

申请号：US17092543

申请日：2020-11-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Hsien Chiang ,  Yu-Chih Huang ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai ,  Chiahung Liu ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/3171 ,  H01L21/565 ,  H01L21/76837 ,  H01L23/528 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/02373

摘要： In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

公开(公告)号：US11705411B2

公开(公告)日：2023-07-18

申请号：US17315921

申请日：2021-05-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Ping Chiang ,  Yi-Che Chiang ,  Nien-Fang Wu ,  Min-Chien Hsiao ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q21/00 ,  H01L21/56 ,  H01L23/538 ,  H01Q1/22 ,  H01Q21/22

CPC分类号： H01L23/66 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L25/0655 ,  H01Q9/045 ,  H01Q21/0087 ,  H01Q21/065 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/5389 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01Q21/0075 ,  H01Q21/22 ,  H01L2224/97 ,  H01L2224/83

摘要： Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.

公开(公告)号：US20230009901A1

公开(公告)日：2023-01-12

申请号：US17371110

申请日：2021-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hsun Chen ,  Chien-Hsun Lee ,  Chung-Shi Liu ,  Jiun-Yi Wu ,  Shou-Yi Wang ,  Tsung-Ding Wang

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

摘要： A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

公开(公告)号：US11538761B2

公开(公告)日：2022-12-27

申请号：US17144061

申请日：2021-01-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hao-Cheng Hou ,  Wei-Yu Chen ,  Jung-Wei Cheng ,  Tsung-Ding Wang ,  Chien-Hsun Lee ,  Chung-Shi Liu

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/18

摘要： A semiconductor package includes a first semiconductor die, a molded die, a third encapsulant, and a redistribution structure. The molded die includes a chip, a first encapsulant, and a second encapsulant. The first encapsulant laterally wraps the chip. The second encapsulant laterally wraps the first encapsulant. The third encapsulant laterally wraps the first semiconductor die and the molded die. The redistribution structure extends on the second encapsulant, the third encapsulant, and the first semiconductor die. The redistribution structure is electrically connected to the first semiconductor die and the molded die. The second encapsulant separates the first encapsulant from the third encapsulant.

公开(公告)号：US20220382004A1

公开(公告)日：2022-12-01

申请号：US17332988

申请日：2021-05-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Ming Weng ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Hung-Yi Kuo ,  Tsung-Yuan Yu ,  Hua-Kuei Lin ,  Yu-Hsiang Hu ,  Chewn-Pu Jou ,  Feng-Wei Kuo

IPC分类号： G02B6/43 ,  G02B6/42

摘要： An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.