Invention Grant
- Patent Title: Scheduling memory accesses using an efficient row burst value
- Patent Title (中): 使用有效的行突发值调度存储器访问
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Application No.: US13917033Application Date: 2013-06-13
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Publication No.: US09489321B2Publication Date: 2016-11-08
- Inventor: James M. O'Connor , Niladrish Chatterjee , Nuwan S. Jayasena , Gabriel H. Loh
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Polansky & Associates, P.L.L.C.
- Agent Paul J. Polansky
- Main IPC: G06F13/16
- IPC: G06F13/16

Abstract:
A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.
Public/Granted literature
- US20140372711A1 SCHEDULING MEMORY ACCESSES USING AN EFFICIENT ROW BURST VALUE Public/Granted day:2014-12-18
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