公开(公告)号：US09489321B2

公开(公告)日：2016-11-08

申请号：US13917033

申请日：2013-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Niladrish Chatterjee ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/161 ,  G06F13/1694

Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.

Abstract translation: 存储器访问代理包括存储器访问生成电路和存储器控制器。 存储器访问生成电路适于以第一有序布置生成多个存储器访问。 存储器控制器耦合到存储器存取产生电路，并且具有输出端口，用于基于存储器访问和外部存储器的特性以第二有序布置提供对输出端口的多个存储器访问。 存储器控制器通过计算有效的行脉冲串值和中断多个行命中请求来基于有效的行脉冲串值来调度行错请求来确定第二排序。

公开(公告)号：US20140173225A1

公开(公告)日：2014-06-19

申请号：US13719710

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Niladrish Chatterjee ,  James O'Connor ,  Gabriel Loh ,  Nuwan Jayasena

IPC: G06F12/00

CPC classification number: G06F9/3887 ,  G06F9/3824

Abstract: Apparatus, computer readable medium, and method of servicing memory requests are presented. A first plurality of memory requests are associated together, wherein each of the first plurality of memory requests is generated by a corresponding one of a first plurality of processors, and wherein each of the first plurality of processors is executing a first same instruction. A second plurality of memory requests are associated together, wherein each of the second plurality of memory requests is generated by a corresponding one of a second plurality of processors, and wherein each of the second plurality of processors is executing a second same instruction. A determination is made to service the first plurality of memory requests before the second plurality of memory requests and the first plurality of memory requests is serviced before the second plurality of memory requests.

Abstract translation: 提供了设备，计算机可读介质和服务存储器请求的方法。 第一多个存储器请求被关联在一起，其中第一多个存储器请求中的每一个由第一多个处理器中的对应的一个处理器生成，并且其中第一多个处理器中的每一个正在执行第一个相同的指令。 第二多个存储器请求被关联在一起，其中第二多个存储器请求中的每一个由第二多个处理器中的对应的一个处理器生成，并且其中第二多个处理器中的每一个正在执行第二个相同的指令。 确定在第二多个存储器请求之前服务第一多个存储器请求，并且在第二多个存储器请求之前服务第一多个存储器请求。

公开(公告)号：US09910605B2

公开(公告)日：2018-03-06

申请号：US15353431

申请日：2016-11-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/0811

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

公开(公告)号：US20140372711A1

公开(公告)日：2014-12-18

申请号：US13917033

申请日：2013-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Niladrish Chatterjee ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/161 ,  G06F13/1694

Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.

Abstract translation: 存储器访问代理包括存储器访问生成电路和存储器控制器。 存储器访问生成电路适于以第一有序布置生成多个存储器访问。 存储器控制器耦合到存储器存取产生电路，并且具有输出端口，用于基于存储器访问和外部存储器的特性以第二有序布置提供对输出端口的多个存储器访问。 存储器控制器通过计算有效的行脉冲串值和中断多个行命中请求来基于有效的行脉冲串值来调度行错请求来确定第二排序。

公开(公告)号：US20140177347A1

公开(公告)日：2014-06-26

申请号：US13721315

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Niladrish Chatterjee ,  James O'Connor ,  Nuwan Jayasena ,  Gabriel Loh

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C2207/2236

Abstract: A method and apparatus for inter-row data transfer in memory devices is described. Data transfer from one physical location in a memory device to another is achieved without engaging the external input/output pins on the memory device. In an example method, a memory device is responsive to a row transfer (RT) command which includes a source row identifier and a target row identifier. The memory device activates a source row and storing source row data in a row buffer, latches the target row identifier into the memory device, activates a word line of a target row to prepare for a write operation, and stores the source row data from the row buffer into the target row.

Abstract translation: 描述了存储器件中行间数据传输的方法和装置。 从存储设备中的一个物理位置到另一物理位置的数据传输是在不将外部输入/输出引脚接入存储器件的情况下实现的。 在示例性方法中，存储器设备响应于包括源行标识符和目标行标识符的行传送（RT）命令。 存储器件激活源行并且将源行数据存储在行缓冲器中，将目标行标识符锁存到存储器件中，激活目标行的字线以准备写入操作，并存储源行数据 行缓冲区到目标行。

公开(公告)号：US20170160955A1

公开(公告)日：2017-06-08

申请号：US15353431

申请日：2016-11-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

公开(公告)号：US09535831B2

公开(公告)日：2017-01-03

申请号：US14152003

申请日：2014-01-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F12/08 ,  G11C11/00 ,  G06F12/06

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

Abstract translation: 芯片堆叠的混合存储器设备实现实现第一存储器架构类型的第一存储器单元电路的一个或多个存储器管芯的第一组和执行第二存储器架构类型不同的第二存储器单元电路的一个或多个存储器管芯的第二组 比第一个内存架构类型。 芯片堆叠式混合存储器件还包括电耦合到一个或多个存储器管芯的第一和第二组的一个或多个逻辑管芯组，该组一个或多个逻辑管芯包括存储器接口和页迁移管理器， 所述存储器接口可耦合到所述管芯堆叠式混合存储器件外部的器件，以及所述页面迁移管理器，用于在所述第一组一个或多个存储器管芯与所述第二组一个或多个存储器管芯之间传送存储器页。

公开(公告)号：US20150199126A1

公开(公告)日：2015-07-16

申请号：US14152003

申请日：2014-01-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

Abstract translation: 芯片堆叠的混合存储器设备实现实现第一存储器架构类型的第一存储器单元电路的一个或多个存储器管芯的第一组和执行第二存储器架构类型不同的第二存储器单元电路的一个或多个存储器管芯的第二组 比第一个内存架构类型。 芯片堆叠式混合存储器件还包括电耦合到一个或多个存储器管芯的第一和第二组的一个或多个逻辑管芯组，该组一个或多个逻辑管芯包括存储器接口和页迁移管理器， 所述存储器接口可耦合到所述管芯堆叠式混合存储器件外部的器件，以及所述页面迁移管理器，用于在所述第一组一个或多个存储器管芯与所述第二组一个或多个存储器管芯之间传送存储器页。