Invention Grant
- Patent Title: Two level re-order buffer
- Patent Title (中): 两级重新排序缓冲区
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Application No.: US14040016Application Date: 2013-09-27
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Publication No.: US09495159B2Publication Date: 2016-11-15
- Inventor: Mark J. Dechene , Srikanth T. Srinivasan , Matthew C. Merten , Tong Li , Christine E. Wang
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Andrews Kurth Kenyon LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/46
Abstract:
In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.
Public/Granted literature
- US20150095627A1 TWO LEVEL RE-ORDER BUFFER Public/Granted day:2015-04-02
Information query
