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    Processor prefetch throttling based on short streams
    1.
    发明授权
    Processor prefetch throttling based on short streams 有权

    公开(公告)号：US10379864B2

    公开(公告)日：2019-08-13

    申请号：US15390588

    申请日：2016-12-26

    Applicant: Intel Corporation

    Inventor： Chunhui Zhang ,  Seth H. Pugsley ,  Mark J. Dechene

    IPC: G06F9/305 ,  G06F9/34 ,  G06F12/08 ,  G06F9/38 ,  G06F9/345 ,  G06F9/30 ,  G06F9/355 ,  G06F12/0862

    Abstract: In an embodiment, a processor comprises a prefetch history array and a prefetch circuit. The prefetch history array comprises a plurality of entries corresponding to prefetch addresses, each entry of the plurality of entries comprising a sublength value associated with a frequency that a stride is repeated. The prefetch circuit is to: for each entry of the plurality of entries, adjust the sublength value based on stride matches for an address of the entry; adjust a short stream counter based on the sublength values of the plurality of entries in the prefetch history array; determine whether the short stream counter has exceeded a throttling threshold; and in response to a determination that the short stream counter has exceeded the throttling threshold, throttle a prefetch level of the prefetch circuit. Other embodiments are described and claimed.

    Systems and methods to predict load data values
    2.
    发明授权
    Systems and methods to predict load data values 有权

    公开(公告)号：US10761844B2

    公开(公告)日：2020-09-01

    申请号：US16023407

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Manjunath Shevgoor ,  Mark J. Dechene ,  Stanislav Shwartsman ,  Pavel I. Kryukov

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/1027

    Abstract: Disclosed embodiments relate to predicting load data. In one example, a processor a pipeline having stages ordered as fetch, decode, allocate, write back, and commit, a training table to store an address, predicted data, a state, and a count of instances of unchanged return data, and tracking circuitry to determine, during one or more of the allocate and decode stages, whether a training table entry has a first state and matches a fetched first load instruction, and, if so, using the data predicted by the entry during the execute stage, the tracking circuitry further to update the training table during or after the write back stage to set the state of the first load instruction in the training table to the first state when the count reaches a first threshold.

    Supporting binary translation alias detection in an out-of-order processor
    3.
    发明授权
    Supporting binary translation alias detection in an out-of-order processor 有权

    公开(公告)号：US10228956B2

    公开(公告)日：2019-03-12

    申请号：US15282266

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Vineeth Mekkat ,  Mark J. Dechene ,  Zhongying Zhang ,  Jason Agron ,  Sebastian Winkel

    IPC: G06F9/312 ,  G06F9/44 ,  G06F9/455 ,  G06F9/38 ,  G06F8/41 ,  G06F8/52 ,  G06F9/30

    Abstract: In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.

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