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公开(公告)号：US10896141B2
公开(公告)日：2021-01-19
申请号：US16364725
申请日：2019-03-26
Applicant: Intel Corporation
Inventor： Jeffrey J. Cook , Jonathan D. Pearce , Srikanth T. Srinivasan , Rishiraj A. Bheda , David B. Sheffield , Abhijit Davare , Anton Alexandrovich Sorokin
IPC: G06F13/16 , G06F9/38 , H04L9/06 , G06F12/0815
Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.
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公开(公告)号：US20200310992A1
公开(公告)日：2020-10-01
申请号：US16364725
申请日：2019-03-26
Applicant: Intel Corporation
Inventor： Jeffrey J. Cook , Jonathan D. Pearce , Srikanth T. Srinivasan , Rishiraj A. Bheda , David B. Sheffield , Abhijit Davare , Anton Alexandrovich Sorokin
IPC: G06F13/16 , G06F9/38 , G06F12/0815 , H04L9/06
Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.
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3.发明申请公开(公告)号：US20200310817A1
公开(公告)日：2020-10-01
申请号：US16364704
申请日：2019-03-26
Applicant: Intel Corporation
Inventor： Jeffrey J. Cook , Srikanth T. Srinivasan , Jonathan D. Pearce , David B. Sheffield
Abstract: In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.
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公开(公告)号：US09904553B2
公开(公告)日：2018-02-27
申请号：US15159040
申请日：2016-05-19
Applicant: Intel Corporation
Inventor： Bambang Sutanto , Srikanth T. Srinivasan , Matthew C. Merten , Chia Yin Kevin Lai , Ammon J Christiansen , Justin M. Deinlein
CPC classification number: G06F9/384 , G06F9/3836 , G06F9/3855 , G06F9/4881
Abstract: A processor and method are described for scheduling operations for execution within a reservation station. For example, a method in accordance with one embodiment of the invention includes the operations of: classifying a plurality of operations based on the execution ports usable to execute those operations; allocating the plurality of operations into groups within a reservation station based on the classification, wherein each group is serviced by one or more execution ports corresponding to the classification, and wherein two or more entries within a group share a common read port and a common write port; dynamically scheduling two or more operations in a group for concurrent execution based on the ports capable of executing those operations and a relative age of the operations.
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5.发明授权公开(公告)号：US09372698B2
公开(公告)日：2016-06-21
申请号：US13931864
申请日：2013-06-29
Applicant: INTEL CORPORATION
Inventor： Bambang Sutanto , Srikanth T. Srinivasan , Matthew C. Merten , Chia Yin Kevin Lai , Ammon J Christiansen , Justin M Deinlein
CPC classification number: G06F9/384 , G06F9/3836 , G06F9/3855 , G06F9/4881
Abstract: A processor and method are described for scheduling operations for execution within a reservation station. For example, a method in accordance with one embodiment of the invention includes the operations of: classifying a plurality of operations based on the execution ports usable to execute those operations; allocating the plurality of operations into groups within a reservation station based on the classification, wherein each group is serviced by one or more execution ports corresponding to the classification, and wherein two or more entries within a group share a common read port and a common write port; dynamically scheduling two or more operations in a group for concurrent execution based on the ports capable of executing those operations and a relative age of the operations.
Abstract translation: 描述了用于在保留站内执行的调度操作的处理器和方法。 例如，根据本发明的一个实施例的方法包括以下操作：基于可用于执行这些操作的执行端口对多个操作进行分类; 基于分类，将多个操作分配到保留站内的组中，其中每个组由对应于分类的一个或多个执行端口服务，并且其中组内的两个或多个条目共享公共读取端口和公共写入 港口; 基于能够执行这些操作的端口和操作的相对年龄，动态地调度用于并发执行的组中的两个或更多个操作。
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Patent Agency Ranking
公开(公告)号：US20200310815A1
公开(公告)日：2020-10-01
申请号：US16364688
申请日：2019-03-26
Applicant: Intel Corporation
Inventor： Andrey Ayupov , Srikanth T. Srinivasan , Jonathan D. Pearce , David B. Sheffield
Abstract: In one embodiment, an apparatus includes: a plurality of registers; a first instruction queue to store first instructions; a second instruction queue to store second instructions; a program order queue having a plurality of portions each associated with one of the plurality of registers, each of the portions having entries to store a state of an instruction, the state comprising an encoding of a use of the register by the instruction and a source instruction queue for the instruction; and a dispatcher to dispatch for execution the first and second instructions from the first and second instruction queues based at least in part on information stored in the program order queue, to manage instruction dependencies between the first instructions and the second instructions. Other embodiments are described and claimed.
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7.发明授权公开(公告)号：US11188341B2
公开(公告)日：2021-11-30
申请号：US16364704
申请日：2019-03-26
Applicant: Intel Corporation
Inventor： Jeffrey J. Cook , Srikanth T. Srinivasan , Jonathan D. Pearce , David B. Sheffield
Abstract: In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.
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公开(公告)号：US11243775B2
公开(公告)日：2022-02-08
申请号：US16364688
申请日：2019-03-26
Applicant: Intel Corporation
Inventor： Andrey Ayupov , Srikanth T. Srinivasan , Jonathan D. Pearce , David B. Sheffield
IPC: G06F9/38
Abstract: In one embodiment, an apparatus includes: a plurality of registers; a first instruction queue to store first instructions; a second instruction queue to store second instructions; a program order queue having a plurality of portions each associated with one of the plurality of registers, each of the portions having entries to store a state of an instruction, the state comprising an encoding of a use of the register by the instruction and a source instruction queue for the instruction; and a dispatcher to dispatch for execution the first and second instructions from the first and second instruction queues based at least in part on information stored in the program order queue, to manage instruction dependencies between the first instructions and the second instructions. Other embodiments are described and claimed.
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公开(公告)号：US10418098B2
公开(公告)日：2019-09-17
申请号：US15857340
申请日：2017-12-28
Applicant: Intel Corporation
Inventor： Srikanth T. Srinivasan , Shigeki Tomishima
Abstract: Devices for computing the sum of multiple Vector-Vector Dot-Products (VVDP) or multiple partial sums of VVDP can include a resistive memory array and a reduction circuit. The reduction circuit can be configured to determine a sum of a selected one or more of a plurality of bit lines of the resistive memory array. A VVDP reduction can be determined from the sum of the selected one or more of the plurality of bit lines.
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公开(公告)号：US20180011748A1
公开(公告)日：2018-01-11
申请号：US15699823
申请日：2017-09-08
Applicant: Intel Corporation
Inventor： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
CPC classification number: G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859
Abstract: A method and apparatus for post-retire transaction access tracking is herein described. Load and store buffers are capable of storing senior entries. In the load buffer a first access is scheduled based on a load buffer entry. Tracking information associated with the load is stored in a filter field in the load buffer entry. Upon retirement, the load buffer entry is marked as a senior load entry. A scheduler schedules a post-retire access to update transaction tracking information, if the filter field does not represent that the tracking information has already been updated during a pendency of the transaction. Before evicting a line in a cache, the load buffer is snooped to ensure no load accessed the line to be evicted.
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