公开(公告)号：US10331452B2

公开(公告)日：2019-06-25

申请号：US14126313

申请日：2013-06-27

Applicant: Intel Corporation

Inventor： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

IPC: G06F9/30 ,  G06F11/36

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

公开(公告)号：US11531542B2

公开(公告)日：2022-12-20

申请号：US17393361

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret L. Toll

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US20210365264A1

公开(公告)日：2021-11-25

申请号：US17393361

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret T. Toll, I

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US09753832B2

公开(公告)日：2017-09-05

申请号：US13930501

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Ilya Wagner ,  Matthew C. Merten ,  Frank Binns ,  Christine E. Wang ,  Mayank Bomb ,  Tong Li ,  Thilo Schmitt ,  M D A. Rahman

IPC: G06F9/30 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/348 ,  G06F2201/81

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

公开(公告)号：US20220027154A1

公开(公告)日：2022-01-27

申请号：US17496632

申请日：2021-10-07

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret T. Toll, I

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US09495159B2

公开(公告)日：2016-11-15

申请号：US14040016

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Mark J. Dechene ,  Srikanth T. Srinivasan ,  Matthew C. Merten ,  Tong Li ,  Christine E. Wang

IPC: G06F9/30 ,  G06F9/46

CPC classification number: G06F9/30145 ,  G06F8/445 ,  G06F8/47 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/45508 ,  G06F9/461

Abstract: In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.

Abstract translation: 响应于检测到一个或多个条件被满足，可以创建线程的当前状态的检查点。 可以将一个或多个不完整的指令从重新排序缓冲器的第一级移动到重新排序缓冲器的第二级。 每个不完整的指令可能正在执行或等待执行。