Invention Grant
- Patent Title: Recess and epitaxial layer to improve transistor performance
- Patent Title (中): 凹槽和外延层,以提高晶体管的性能
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Application No.: US14208438Application Date: 2014-03-13
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Publication No.: US09536746B2Publication Date: 2017-01-03
- Inventor: Yeh Hsu , Chia-Wen Liu , Tsung-Hsing Yu , Ken-Ichi Goto , Shih-Syuan Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/306 ; H01L21/28 ; H01L29/66 ; H01L29/10 ; H01L21/3065 ; H01L29/165

Abstract:
Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.
Public/Granted literature
- US20150263171A1 RECESS AND EPITAXIAL LAYER TO IMPROVE TRANSISTOR PERFORMANCE Public/Granted day:2015-09-17
Information query
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