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    Transistor design
    3.
    发明授权
    Transistor design 有权
    晶体管设计

    公开(公告)号：US09184234B2

    公开(公告)日：2015-11-10

    申请号：US14156546

    申请日：2014-01-16

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Wen-Yuan Chen ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L21/00 ,  H01L29/00 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/36 ,  H01L29/16 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L29/167

    CPC分类号： H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

    摘要： Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

    摘要翻译： 本公开的一些实施例涉及形成在包含第一杂质类型的掺杂杂质的半导体衬底中的晶体管器件。 该晶体管器件包括由包括第一杂质类型的掺杂杂质的δ掺杂层构成的沟道，并且被配置为在沟道内产生峰值掺杂剂浓度。 通道还包括覆盖在δ掺杂层上的含碳材料层，并且被配置为防止掺杂剂从δ-掺杂层和半导体衬底的反向扩散。 通道还包括覆盖在含碳材料层上的衬底材料层，并且被配置为在通道的表面附近实现陡峭的逆向掺杂剂浓度分布。 在一些实施例中，反掺杂层位于配置成减少半导体衬底内的泄漏的δ掺杂层的下面，并且包括与第一杂质类型相反的第二杂质类型的掺杂杂质。

    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR
    4.
    发明申请
    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR 有权

    公开(公告)号：US20210343787A1

    公开(公告)日：2021-11-04

    申请号：US17078583

    申请日：2020-10-23

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Ken-Ichi Goto ,  Chung-Te Lin ,  Mauricio Manfrini

    IPC分类号： H01L27/22 ,  H01L27/24

    摘要： The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.

    Recess and epitaxial layer to improve transistor performance
    7.
    发明授权
    Recess and epitaxial layer to improve transistor performance 有权
    凹槽和外延层，以提高晶体管的性能

    公开(公告)号：US09536746B2

    公开(公告)日：2017-01-03

    申请号：US14208438

    申请日：2014-03-13

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Yeh Hsu ,  Chia-Wen Liu ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Shih-Syuan Huang

    IPC分类号： H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3065 ,  H01L29/165

    CPC分类号： H01L21/30604 ,  H01L21/28123 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

    摘要： Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.

    摘要翻译： 本公开的一些实施例涉及被配置为抵抗寄生耦合的半导体器件，同时保持对比较窄的晶体管的阈值电压控制。 在一些实施例中，形成在半导体衬底上的半导体器件。 半导体器件包括沟道，其包括在半导体衬底的表面上形成生长的外延层，以及形成在外延层上的栅极材料。 在一些实施例中，公开了一种形成半导体器件的方法。 该方法包括蚀刻半导体衬底的表面以在第一和第二隔离结构之间形成凹陷，在凹槽内形成外延层，其在半导体衬底的表面上形成生长，并在外延层上形成栅极材料。 还公开了其他实施例。

    Epitaxial channel with a counter-halo implant to improve analog gain
    8.
    发明授权
    Epitaxial channel with a counter-halo implant to improve analog gain 有权
    具有反向晕轮植入的外延通道，以改善模拟增益

    公开(公告)号：US09425099B2

    公开(公告)日：2016-08-23

    申请号：US14156496

    申请日：2014-01-16

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

    CPC分类号： H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

    摘要： Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors.

    摘要翻译： 本公开的一些实施例涉及一种改善长沟道晶体管性能的植入物，对短沟道晶体管性能几乎没有影响。 为了减轻DIBL，衬底上的长沟道晶体管和短沟道晶体管都经历晕圈植入。 虽然光晕植入改善了短沟道晶体管的性能，但是它会降低长沟道晶体管的性能。 因此，仅在长沟道晶体管上执行反向注入才能恢复其性能。 为了实现这一点，反向注入以在长沟道晶体管的源极/漏极区附近引入掺杂剂杂质以抵消晕轮植入物的影响的角度进行，而反向晕轮植入物同时被遮蔽而达到 短沟道晶体管的通道。

    Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices
    10.
    发明申请
    Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices 有权
    位错应力记忆技术（DSMT）在外延通道器件上的应用

    公开(公告)号：US20150295085A1

    公开(公告)日：2015-10-15

    申请号：US14252147

    申请日：2014-04-14

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

    IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

    CPC分类号： H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

    摘要： The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance.

    摘要翻译： 本公开涉及具有外延源极和漏极区域的晶体管器件，其具有向外延沟道区域提供应力的位错应力存储（DSM）区域和相关联的形成方法。 晶体管器件具有设置在半导体衬底上的外延层，以及设置在外延层上的栅极结构。 沟道区域在位于栅极结构的相对侧的外延源极和漏极区域之间的栅极结构的下方延伸。 第一和第二位错应力记忆（DSM）区域具有在沟道区域内产生应力的应力晶格。 第一和第二DSM区域分别从外延源区域的下面延伸到外延源区域内的从外延漏极区域下方的第一位置到外延漏极区域内的第二位置。 使用第一和第二DSM区域来压缩通道区域，提高了设备​​性能。