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    Counter pocket implant to improve analog gain
    7.
    发明授权
    Counter pocket implant to improve analog gain 有权
    计数器口袋种植体，以提高模拟增益

    公开(公告)号：US09252236B2

    公开(公告)日：2016-02-02

    申请号：US14222759

    申请日：2014-03-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Syuan Huang ,  Tsung-Hsing Yu ,  Yi-Ming Sheu

    IPC: H01L21/265 ,  H01L29/66 ,  H01L29/10

    CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A method for improving analog gain in long channel devices associated with a semiconductor workpiece is provided. A gate oxide layer is formed on the semiconductor workpiece, and a plurality of gate structures are formed over the gate oxide layer, wherein a first pair of the plurality of gate structures define a short channel device region and a second pair of the plurality of gate structures define a long channel device region. A first ion implantation with a first dopant is performed at a first angle, wherein the first dopant is one of an n-type dopant and a p-type dopant. A second ion implantation with a second dopant is performed at a second angle, wherein the second angle is greater than the first angle. The second dopant is one or an n-type dopant and a p-type dopant that is opposite of the first dopant, and a height of the plurality of gate structures and the second angle generally prevents the second ion implantation from implanting ions into the short channel device region.

    Abstract translation: 提供了一种用于改善与半导体工件相关联的长通道器件中的模拟增益的方法。 在半导体工件上形成栅极氧化层，并且在栅极氧化物层上形成多个栅极结构，其中多个栅极结构中的第一对限定短沟道器件区域和第二对多个栅极 结构定义了一个长通道器件区域。 以第一角度执行具有第一掺杂剂的第一离子注入，其中第一掺杂剂是n型掺杂剂和p型掺杂剂之一。 以第二角度执行具有第二掺杂剂的第二离子注入，其中第二角度大于第一角度。 第二掺杂剂是与第一掺杂剂相反的一种或n型掺杂剂和p型掺杂剂，并且多个栅极结构的高度和第二角度通常防止第二离子注入将离子注入到短路中 通道设备区域。

    Recess and epitaxial layer to improve transistor performance
    9.
    发明授权
    Recess and epitaxial layer to improve transistor performance 有权
    凹槽和外延层，以提高晶体管的性能

    公开(公告)号：US09536746B2

    公开(公告)日：2017-01-03

    申请号：US14208438

    申请日：2014-03-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yeh Hsu ,  Chia-Wen Liu ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Shih-Syuan Huang

    IPC: H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3065 ,  H01L29/165

    CPC classification number: H01L21/30604 ,  H01L21/28123 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

    Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.

    Abstract translation: 本公开的一些实施例涉及被配置为抵抗寄生耦合的半导体器件，同时保持对比较窄的晶体管的阈值电压控制。 在一些实施例中，形成在半导体衬底上的半导体器件。 半导体器件包括沟道，其包括在半导体衬底的表面上形成生长的外延层，以及形成在外延层上的栅极材料。 在一些实施例中，公开了一种形成半导体器件的方法。 该方法包括蚀刻半导体衬底的表面以在第一和第二隔离结构之间形成凹陷，在凹槽内形成外延层，其在半导体衬底的表面上形成生长，并在外延层上形成栅极材料。 还公开了其他实施例。

    Epitaxial channel with a counter-halo implant to improve analog gain
    10.
    发明授权
    Epitaxial channel with a counter-halo implant to improve analog gain 有权
    具有反向晕轮植入的外延通道，以改善模拟增益

    公开(公告)号：US09425099B2

    公开(公告)日：2016-08-23

    申请号：US14156496

    申请日：2014-01-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

    CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

    Abstract: Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors.

    Abstract translation: 本公开的一些实施例涉及一种改善长沟道晶体管性能的植入物，对短沟道晶体管性能几乎没有影响。 为了减轻DIBL，衬底上的长沟道晶体管和短沟道晶体管都经历晕圈植入。 虽然光晕植入改善了短沟道晶体管的性能，但是它会降低长沟道晶体管的性能。 因此，仅在长沟道晶体管上执行反向注入才能恢复其性能。 为了实现这一点，反向注入以在长沟道晶体管的源极/漏极区附近引入掺杂剂杂质以抵消晕轮植入物的影响的角度进行，而反向晕轮植入物同时被遮蔽而达到 短沟道晶体管的通道。

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