公开(公告)号：US11145762B2

公开(公告)日：2021-10-12

申请号：US16016748

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US11955554B2

公开(公告)日：2024-04-09

申请号：US17812997

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/7848

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

公开(公告)号：US09536746B2

公开(公告)日：2017-01-03

申请号：US14208438

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yeh Hsu ,  Chia-Wen Liu ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Shih-Syuan Huang

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3065 ,  H01L29/165

CPC classification number: H01L21/30604 ,  H01L21/28123 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.

Abstract translation: 本公开的一些实施例涉及被配置为抵抗寄生耦合的半导体器件，同时保持对比较窄的晶体管的阈值电压控制。 在一些实施例中，形成在半导体衬底上的半导体器件。 半导体器件包括沟道，其包括在半导体衬底的表面上形成生长的外延层，以及形成在外延层上的栅极材料。 在一些实施例中，公开了一种形成半导体器件的方法。 该方法包括蚀刻半导体衬底的表面以在第一和第二隔离结构之间形成凹陷，在凹槽内形成外延层，其在半导体衬底的表面上形成生长，并在外延层上形成栅极材料。 还公开了其他实施例。

公开(公告)号：US09224814B2

公开(公告)日：2015-12-29

申请号：US14156515

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Yeh Hsu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7836 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.

Abstract translation: 本公开涉及一种形成具有提供电压阈值的低变化的碳注入区域的晶体管器件的方法和相关联的器件。 该方法通过在半导体衬底内形成阱区进行。 选择性地蚀刻半导体衬底以在阱区内形成凹陷。 在形成凹部之后，选择性地进行碳注入，以在凹部下方的位置在半导体衬底内形成碳注入区域。 然后进行外延生长以在覆盖碳注入区域的位置处在凹槽内形成一个或多个外延层。 源极和漏极区域随后形成在半导体衬底内，使得包括一个或多个外延层的沟道区域将源极/漏极彼此分离。

公开(公告)号：US20150263171A1

公开(公告)日：2015-09-17

申请号：US14208438

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yeh Hsu ,  Chia-Wen Liu ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Shih-Syuan Huang

IPC: H01L29/78 ,  H01L21/263 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/28123 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.

Abstract translation: 本公开的一些实施例涉及被配置为抵抗寄生耦合的半导体器件，同时保持对比较窄的晶体管的阈值电压控制。 在一些实施例中，形成在半导体衬底上的半导体器件。 半导体器件包括沟道，其包括在半导体衬底的表面上形成生长的外延层，以及形成在外延层上的栅极材料。 在一些实施例中，公开了一种形成半导体器件的方法。 该方法包括蚀刻半导体衬底的表面以在第一和第二隔离结构之间形成凹陷，在凹槽内形成外延层，其在半导体衬底的表面上形成生长，并在外延层上形成栅极材料。 还公开了其他实施例。

公开(公告)号：US11152338B2

公开(公告)日：2021-10-19

申请号：US16889498

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang Wu ,  Chun-Fu Cheng ,  Chung-Cheng Wu ,  Yi-Han Wang ,  Chia-Wen Liu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L25/065 ,  H01L21/02 ,  H01L25/04 ,  H01L29/08 ,  H01L29/06 ,  H01L27/06 ,  H01L29/40 ,  H01L29/78 ,  B82Y99/00 ,  B82Y10/00

Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

公开(公告)号：US10672742B2

公开(公告)日：2020-06-02

申请号：US15794286

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang Wu ,  Chun-Fu Cheng ,  Chung-Cheng Wu ,  Yi-Han Wang ,  Chia-Wen Liu

IPC: H01L29/66 ,  H01L25/065 ,  H01L21/02 ,  H01L25/04 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L27/06 ,  H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  B82Y99/00 ,  B82Y10/00

Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.

公开(公告)号：US10008603B2

公开(公告)日：2018-06-26

申请号：US15355844

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78654 ,  H01L29/78696

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.

公开(公告)号：US09525031B2

公开(公告)日：2016-12-20

申请号：US14208353

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Chia-Wen Liu ,  Yeh Hsu

IPC: H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02535 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel. The replacement channel region provides improved drive current, thereby enabling better performance and higher yield.

Abstract translation: 本公开的一些实施例涉及晶体管内的外延生长的替换沟道区，其由于制造工艺的波动而减轻晶体管的沟道内的变化。 替换通道区域通过使半导体衬底的源极/漏极和沟道区域凹陷形成，并且在凹槽内外延生长置换沟道区域，其包括在凹部的底表面上外延生长下部外延沟道区域，并且外延生长 在所述凹部的底表面上方的上部外延沟道区域。 下部外延沟道区域从上部外延沟道区域延迟掺杂剂反向扩散，导致替代沟道区域内的陡峭的逆向掺杂物分布。 上部外延沟道区增加了沟道内的载流子迁移率。 替代通道区域提供改善的驱动电流，从而实现更好的性能和更高的产量。

公开(公告)号：US20160064560A1

公开(公告)日：2016-03-03

申请号：US14935760

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Yeh Hsu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7836 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

Abstract translation: 本发明涉及一种具有提供低电压阈值变化的外延碳层和/或碳注入区域的晶体管器件以及相关的形成方法。 在一些实施例中，晶体管器件具有布置在半导体衬底内的凹槽内的外延区域。 外延区域具有碳掺杂硅外延层和设置在掺碳硅外延层上的硅外延层。 栅极结构布置在硅外延层的上方。 栅极结构具有设置在硅外延层上的栅极介电层和设置在栅极介电层上的栅极电极层。 源极区域和漏极区域布置在设置在栅极结构下方的沟道区域的相对侧上。