Invention Grant
US09571107B2 High-order sigma delta for a divider-less digital phase-locked loop
有权
用于无分频数字锁相环的高阶西格玛delta
- Patent Title: High-order sigma delta for a divider-less digital phase-locked loop
- Patent Title (中): 用于无分频数字锁相环的高阶西格玛delta
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Application No.: US14317435Application Date: 2014-06-27
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Publication No.: US09571107B2Publication Date: 2017-02-14
- Inventor: Rotem Banin , Elan Banin , Ofir Degani
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Forefront IP Lawgroup of Christie and Rivera, PLLC
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/085 ; H04B1/40 ; H03L7/16 ; H03M7/30
Abstract:
Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.
Public/Granted literature
- US20150381188A1 HIGH-ORDER SIGMA DELTA FOR A DIVIDER-LESS DIGITAL PHASE-LOCKED LOOP Public/Granted day:2015-12-31
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