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公开(公告)号：US10027356B2
公开(公告)日：2018-07-17
申请号：US15274509
申请日：2016-09-23
Applicant: Intel IP Corporation
Inventor： Elan Banin , Uri Parker , Ofir Degani , Michael Kerner
Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.
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公开(公告)号：US20180191489A1
公开(公告)日：2018-07-05
申请号：US15395504
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
CPC classification number: H03L7/08 , H03L7/085 , H04L27/0014 , H04L2027/0053 , H04L2027/0067
Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
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3.发明授权公开(公告)号：US09571107B2
公开(公告)日：2017-02-14
申请号：US14317435
申请日：2014-06-27
Applicant: Intel IP Corporation
Inventor： Rotem Banin , Elan Banin , Ofir Degani
CPC classification number: H03L7/085 , H03L7/16 , H03L2207/50 , H03M7/3004 , H04B1/40
Abstract: Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.
Abstract translation: 这里描述的是与无分频数字锁相环（DPLL）的实现相关的技术，其包括与较高阶Σ-Δ匹配的环路响应。
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公开(公告)号：US20200067513A1
公开(公告)日：2020-02-27
申请号：US16465515
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： YAIR DGANI , Michael Kerner , Elan Banin , Nati Dinur , Gil Horovitz , Rotem Banin
Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
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公开(公告)号：US09912357B1
公开(公告)日：2018-03-06
申请号：US15382808
申请日：2016-12-19
Applicant: Intel IP Corporation
Inventor： Uri Parker , Elan Banin , Michael Kerner , Ofir Degani
CPC classification number: H04B1/02 , G11B20/10055 , G11B20/1024 , H02M1/12 , H02P27/08 , H04B1/04 , H04L27/361
Abstract: A digital polar transmitter arrangement having a digital front end (DFE) and a transmit chain is disclosed. The DFE is configured to resample a baseband signal relative to a carrier frequency at a carrier frequency related sample rate, calculate zero crossing positions of the resampled signal, generate delay to time converter (DTC) commands based on the zero crossing positions, calculate amplitude values for the zero crossing positions and generate dynamic phase alignment (DPA) commands based on the amplitude values. The transmit chain is configured to generate an output signal having amplitude and phase modulation based on the DTC and DPA commands.
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Patent Agency Ranking
公开(公告)号：US09698863B2
公开(公告)日：2017-07-04
申请号：US14229812
申请日：2014-03-28
Applicant: Intel IP Corporation
Inventor： Moshe Teplitsky , Michael Genossar , Elan Banin
CPC classification number: H04B1/7101 , H04B1/1027 , H04L25/06 , H04W84/12
Abstract: Logic for spur estimation of a wireless communication packet. Logic may receive an input signal output by a set of analog-to-digital converters and determine means of sequences for each of the analog-to-digital converters. The sequences may be from a preamble of the wireless communication packet. The sequences may comprise a set of short training sequences with an average zero mean received after logic detects a boundary of the sequences. The set of short training sequences may comprise a Golay sequence Ga and a Golay sequence −Ga. Logic may determine spur estimations for each of the analog-to-digital converters based upon a frequency offset estimation for the wireless communication packet. Logic may remove a mean of the spur estimations from the spur estimations. And logic may remove the spur estimations from the packet.
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公开(公告)号：US10263624B2
公开(公告)日：2019-04-16
申请号：US15634183
申请日：2017-06-27
Applicant: Intel IP Corporation
Inventor： Michael Kerner , Elan Banin , Yair Dgani , Evgeny Shumaker , Danniel Nahmanny , Gil Horovitz
Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.
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公开(公告)号：US20190052279A1
公开(公告)日：2019-02-14
申请号：US16077087
申请日：2017-01-24
Applicant: Intel IP Corporation
Inventor： Elan Banin , Tamar Marom , Gil Horovitz , Rotem Banin
IPC: H03L7/091
Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.
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公开(公告)号：US10181856B2
公开(公告)日：2019-01-15
申请号：US15395504
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
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公开(公告)号：US20180091177A1
公开(公告)日：2018-03-29
申请号：US15274509
申请日：2016-09-23
Applicant: Intel IP Corporation
Inventor： Elan Banin , Uri Parker , Ofir Degani , Michael Kerner
CPC classification number: H04B1/0475 , H04B2001/0425 , H04L27/367
Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.
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