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1.发明申请公开(公告)号：US20190253058A1
公开(公告)日：2019-08-15
申请号：US16329312
申请日：2016-09-29
Applicant: INTEL IP CORPORATION
Inventor： Ashoke Ravi , Rotem Banin , Ofir Degani , David Ben-Haim , Yigal Kalmanovich
CPC classification number: H03L7/0995 , H03L7/093 , H03L2207/50 , H04L7/0331 , H04L7/08
Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
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公开(公告)号：US10230520B2
公开(公告)日：2019-03-12
申请号：US15586619
申请日：2017-05-04
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
IPC: H04L27/152 , H04L7/033 , H04B7/06 , H04L27/20 , H04W88/06 , H03L7/16 , H04B7/0413 , H03K5/00
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
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公开(公告)号：US20180175878A1
公开(公告)日：2018-06-21
申请号：US15811721
申请日：2017-11-14
Applicant: Intel IP Corporation
Inventor： Ofir Degani , Rotem Banin , Assaf Ben-Bassat , Sebastian Sievert
CPC classification number: H03M1/82 , H03K5/131 , H03K5/135 , H03K2005/00052 , H03K2005/00058 , H03M1/007 , H04W88/02
Abstract: An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.
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公开(公告)号：US09912357B1
公开(公告)日：2018-03-06
申请号：US15382808
申请日：2016-12-19
Applicant: Intel IP Corporation
Inventor： Uri Parker , Elan Banin , Michael Kerner , Ofir Degani
CPC classification number: H04B1/02 , G11B20/10055 , G11B20/1024 , H02M1/12 , H02P27/08 , H04B1/04 , H04L27/361
Abstract: A digital polar transmitter arrangement having a digital front end (DFE) and a transmit chain is disclosed. The DFE is configured to resample a baseband signal relative to a carrier frequency at a carrier frequency related sample rate, calculate zero crossing positions of the resampled signal, generate delay to time converter (DTC) commands based on the zero crossing positions, calculate amplitude values for the zero crossing positions and generate dynamic phase alignment (DPA) commands based on the amplitude values. The transmit chain is configured to generate an output signal having amplitude and phase modulation based on the DTC and DPA commands.
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公开(公告)号：US20170085365A1
公开(公告)日：2017-03-23
申请号：US14861132
申请日：2015-09-22
Applicant: Intel IP Corporation
Inventor： Ashoke Ravi , Ofir Degani , Rotem Banin , Assaf Ben-Bassat
CPC classification number: H04L7/042 , G04F10/005 , H03K5/135 , H03M1/1061 , H03M1/82 , H04B1/0475 , H04L7/0054
Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.
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Patent Agency Ranking
公开(公告)号：US09407245B2
公开(公告)日：2016-08-02
申请号：US14318857
申请日：2014-06-30
Applicant: Intel IP Corporation
Inventor： Sebastian Sievert , Assaf Ben-Bassat , Ofir Degani , Rotem Banin
IPC: H03K3/027 , H03L7/06 , H03K5/1252 , H03L7/099 , H03L7/081
CPC classification number: H03K5/1252 , H03K5/135 , H03L7/081 , H03L7/0814 , H03L7/0995 , H03L7/0998
Abstract: This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include interpolation cells and retention cells configured provide an interpolated output based on at least two offset clock signals. In certain examples, an example interpolator can provide contention free control of the interpolator output with improved noise immunity.
Abstract translation: 此应用程序除了其他内容之外还讨论了数字时间转换器（DTC）的内插器架构。 在一个示例中，内插器可以包括内插单元和配置的保持单元基于至少两个偏移时钟信号提供内插输出。 在某些示例中，示例性内插器可以提供具有改进的抗噪声能力的内插器输出的无竞争力控制。
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公开(公告)号：US09331722B2
公开(公告)日：2016-05-03
申请号：US14140801
申请日：2013-12-26
Applicant: Intel IP Corporation
Inventor： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala
CPC classification number: H04B17/21 , H03F1/3241 , H03M1/1009 , H03M1/82 , H03M1/84 , H04B1/0475 , H04B2001/0425
Abstract: This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.
Abstract translation: 本文讨论了用于补偿数字到时间转换器（DTC）的非线性的装置和方法。 在一个示例中，无线设备可以包括被配置为从基带处理器接收相位数据信息并提供用于生成无线信号的第一调制信号的数字 - 时间转换器（DTC），检测器配置为接收第一 调制信号并提供DTC的非线性指示，以及被配置为使用非线性指示向DTC提供预失真信息的预失真模块。
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公开(公告)号：US10110245B2
公开(公告)日：2018-10-23
申请号：US15811721
申请日：2017-11-14
Applicant: Intel IP Corporation
Inventor： Ofir Degani , Rotem Banin , Assaf Ben-Bassat , Sebastian Sievert
Abstract: An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.
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公开(公告)号：US20180262383A1
公开(公告)日：2018-09-13
申请号：US15753551
申请日：2015-09-25
Applicant: Intel IP Corporation
Inventor： Sebastian Sievert , Ofir Degani , Ashoke Ravi , Rotem Banin
Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.
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公开(公告)号：US10027356B2
公开(公告)日：2018-07-17
申请号：US15274509
申请日：2016-09-23
Applicant: Intel IP Corporation
Inventor： Elan Banin , Uri Parker , Ofir Degani , Michael Kerner
Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.
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