-
公开(公告)号：US10110245B2
公开(公告)日：2018-10-23
申请号：US15811721
申请日：2017-11-14
Applicant: Intel IP Corporation
Inventor： Ofir Degani , Rotem Banin , Assaf Ben-Bassat , Sebastian Sievert
Abstract: An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.
-
公开(公告)号：US20180262383A1
公开(公告)日：2018-09-13
申请号：US15753551
申请日：2015-09-25
Applicant: Intel IP Corporation
Inventor： Sebastian Sievert , Ofir Degani , Ashoke Ravi , Rotem Banin
Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.
-
公开(公告)号：US20170093556A1
公开(公告)日：2017-03-30
申请号：US14868834
申请日：2015-09-29
Applicant: Intel IP Corporation
Inventor： Ofir Degani , Rotem Banin , Sebastian Sievert
CPC classification number: H04L7/002 , H03F3/2178 , H03F3/245 , H03M1/68 , H03M1/82 , H04L7/0091 , H04L27/365
Abstract: Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second and finer interpolation to increase interpolation ranges. The DTC circuitry generates a fine-phase modulated signal generating at least two correlated signals, and generating coarse and fine interpolations of the correlated signals.
-
4.发明授权公开(公告)号：US09571107B2
公开(公告)日：2017-02-14
申请号：US14317435
申请日：2014-06-27
Applicant: Intel IP Corporation
Inventor： Rotem Banin , Elan Banin , Ofir Degani
CPC classification number: H03L7/085 , H03L7/16 , H03L2207/50 , H03M7/3004 , H04B1/40
Abstract: Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.
Abstract translation: 这里描述的是与无分频数字锁相环（DPLL）的实现相关的技术，其包括与较高阶Σ-Δ匹配的环路响应。
-
5.发明授权Digital-to-time converter and methods for generating phase-modulated signals 有权数字时间转换器和用于产生相位调制信号的方法公开(公告)号：US09071304B2
公开(公告)日：2015-06-30
申请号：US13969132
申请日：2013-08-16
Applicant: Intel IP Corporation
Inventor： Rotem Banin , Ofir Degani , Markus Schimper , Ashoke Ravi
CPC classification number: H04B1/0475 , H03F1/02 , H03F3/24 , H03M1/66 , H03M1/86 , H04B2001/045
Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/−1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.
Abstract translation: 数字 - 时间转换器（DTC）的实施例以及用于产生相位调制信号的方法在这里通常被描述。 在一些实施例中，对振荡器信号进行2N +/- 1次除法产生第一和第二除法器信号，对第一分频器信号进行采样以提供上升沿相关信号，对分频器单元输出信号进行采样以提供下降沿 并且第二除法器信号或第二除法器信号的延迟版本被提供作为除法器单元输出信号。 上升沿和下降沿相关信号之间的选择产生边沿信号。 基于第一和第二边缘信号之间的边缘内插产生精细的相位调制输出信号。
-
Patent Agency Ranking
公开(公告)号：US10707880B2
公开(公告)日：2020-07-07
申请号：US16077087
申请日：2017-01-24
Applicant: Intel IP Corporation
Inventor： Elan Banin , Tamar Marom , Gil Horovitz , Rotem Banin
Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.
-
公开(公告)号：US10686451B2
公开(公告)日：2020-06-16
申请号：US16465515
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Nati Dinur , Gil Horovitz , Rotem Banin
Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
-
公开(公告)号：US10516563B2
公开(公告)日：2019-12-24
申请号：US15753551
申请日：2015-09-25
Applicant: Intel IP Corporation
Inventor： Sebastian Sievert , Ofir Degani , Ashoke Ravi , Rotem Banin
Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.
-
公开(公告)号：US09577684B1
公开(公告)日：2017-02-21
申请号：US14952903
申请日：2015-11-25
Applicant: Intel IP Corporation
Inventor： Sarit Zur , Ofir Degani , Rotem Banin , Assaf Ben-Bassat
CPC classification number: H04B1/0475 , H03C5/00 , H03F1/02 , H03F3/24 , H04B2001/045 , H04L27/361
Abstract: Described herein are technologies related to an implementation of a time interleaved digital-to-time converter (DTC) topology to generate high frequency phase modulated local oscillator (LO) signals. A first and second DTC are connected to an oscillator where outputs of the two DTCs are combined to generate a phase modulated signal and the two DTCs have a frequency rate that is half the frequency rate of the phase modulated signal. The two DTCs can operate at a 50 percent or lower duty cycle.
Abstract translation: 这里描述的是与时间交错数字 - 时间转换器（DTC）拓扑的实施相关的技术，以产生高频相位调制的本地振荡器（LO）信号。 第一和第二DTC连接到振荡器，其中两个DTC的输出被组合以产生相位调制信号，并且两个DTC的频率是相位调制信号的频率的一半。 两个DTC可以在50％或更低的占空比下工作。
-
公开(公告)号：US20200067513A1
公开(公告)日：2020-02-27
申请号：US16465515
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： YAIR DGANI , Michael Kerner , Elan Banin , Nati Dinur , Gil Horovitz , Rotem Banin
Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
-
-
-
-
-
-
-
-
-
Search Results
28
records
(took 0.022 seconds)
