Invention Grant
US09583476B2 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
有权
微电子器件封装,堆叠的微电子器件封装以及用于制造微电子器件的方法
- Patent Title: Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
- Patent Title (中): 微电子器件封装,堆叠的微电子器件封装以及用于制造微电子器件的方法
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Application No.: US15050231Application Date: 2016-02-22
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Publication No.: US09583476B2Publication Date: 2017-02-28
- Inventor: Seng Kim Dalson Ye , Chin Hui Chong
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Priority: SG2005-5523-1 20050826
- Main IPC: H01L25/04
- IPC: H01L25/04 ; H01L25/065 ; H01L25/07 ; H01L25/075 ; H01L25/11 ; H01L25/00 ; H01L23/13 ; H01L23/31 ; H01L23/00 ; H01L21/56 ; H01L25/10

Abstract:
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.
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