公开(公告)号：US20240312890A1

公开(公告)日：2024-09-19

申请号：US18443166

申请日：2024-02-15

申请人： Micron Technology, Inc.

发明人： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  See Hiong Leow ,  Ling Pan ,  Seng Kim Ye ,  Chin Hui Chong

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/181 ,  H01L2924/19011

摘要： At least one embodiment of a semiconductor device assembly include a cross-stack substrate can comprise an assembly substrate including an upper surface, a first and second die stack at the upper surface, and a cross-stack substrate spaced from the upper surface. The first and second die stacks can each include multiple semiconductor dies in electric communication with the assembly substrate, and the cross-stack substrate can be coupled to and extending between a first and a second semiconductor die of the first and second die stacks, respectively. A passive semiconductor component can be carried by the cross-stack substrate, and can be in electric communication with the assembly substrate. Further, the passive semiconductor component can be in electric communication with the first semiconductor die of the first die stack exclusively via the assembly substrate.

公开(公告)号：US11929351B2

公开(公告)日：2024-03-12

申请号：US17682948

申请日：2022-02-28

申请人： Micron Technology, Inc.

发明人： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/48228 ,  H01L2224/48229 ,  H01L2224/85045 ,  H01L2225/0651 ,  H01L2225/06562

摘要： An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

公开(公告)号：US20240072022A1

公开(公告)日：2024-02-29

申请号：US17899592

申请日：2022-08-30

申请人： Micron Technology, Inc.

发明人： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC分类号： H01L25/16 ,  H01G2/06 ,  H01G13/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/16 ,  H01G2/06 ,  H01G13/00 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19105

摘要： Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.

公开(公告)号：US20240071979A1

公开(公告)日：2024-02-29

申请号：US17898368

申请日：2022-08-29

申请人： Micron Technology, Inc.

发明人： Chin Hui Chong ,  Hong Wan Ng ,  Suresh K. Upadhyayula

IPC分类号： H01L23/00

CPC分类号： H01L24/48 ,  H01L24/06 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/06131 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85

摘要： An assembly comprising a substrate with a first and second bond pad at a top surface; and a semiconductor die with a lower surface coupled to the top surface, an upper surface with a third and fourth bond pad thereat, and a side surface perpendicular to the upper and lower surfaces. The first bond pad can be a first distance, the second bond pad can be a second distance, the third bond pad can be a third distance, and the fourth bond pad can be a fourth distance, respectively, from the side surface. The first and third distances summed can be the same as the second and fourth distances summed. A first wire can extend between the first and third bond pads, and a second wire can extend between the second and fourth bond pads.

公开(公告)号：US20230282559A1

公开(公告)日：2023-09-07

申请号：US17686225

申请日：2022-03-03

申请人： Micron Technology, Inc.

发明人： Hong Wan Ng ,  Chin Hui Chong ,  Kelvin Tan Aik Boo ,  Seng Kim Ye

IPC分类号： H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L23/552 ,  H01L23/49816 ,  H01L21/4846 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/08225 ,  H01L2224/80001 ,  H01L2224/48225 ,  H01L2224/48145 ,  H01L2224/49112 ,  H01L2225/06562 ,  H01L2225/06506 ,  H01L2225/0651

摘要： A semiconductor device assembly is provided. The assembly includes a substrate having an upper surface on which is disposed a first device contact, a keep-out region extending from a first side surface of the substrate to a second side surface of the substrate opposite the first, and at least one trace coupled to the first device contact and extending across the keep out region towards a third side surface of the substrate. The assembly further includes at least one semiconductor device disposed over the upper surface of the substrate and coupled to the first device contact. The keep-out region of the substrate is free from conductive structures other than the at least one trace.

公开(公告)号：US11562987B2

公开(公告)日：2023-01-24

申请号：US17232333

申请日：2021-04-16

申请人： Micron Technology, Inc.

发明人： Chin Hui Chong ,  Hong Wan Ng ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

摘要： Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

公开(公告)号：US20210358888A1

公开(公告)日：2021-11-18

申请号：US15931388

申请日：2020-05-13

申请人： Micron Technology, Inc.

发明人： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

摘要： An apparatus includes an integrated circuit and a substrate coupled to the integrated circuit. The substrate includes a primary layer having a first surface that is a first external surface of the substrate. The primary layer includes an open area that extends through the primary layer to an inner layer of the substrate. The substrate includes a secondary layer. The inner layer is located between the primary layer and the secondary layer. The inner layer includes a third surface that is orientated approximately parallel to the first surface of the primary layer. A portion of the third surface of the inner layer is exposed via the open area of the primary layer. A first plurality of wire bond pads are disposed on the portion of the third surface of the inner layer that is exposed via the open area of primary layer.

公开(公告)号：US10861824B2

公开(公告)日：2020-12-08

申请号：US16203555

申请日：2018-11-28

申请人： Micron Technology, Inc.

发明人： Seng Kim Dalson Ye ,  Chin Hui Chong

IPC分类号： H01L25/065 ,  H01L23/13 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/04 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11

摘要： A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

公开(公告)号：US20190096857A1

公开(公告)日：2019-03-28

申请号：US16203555

申请日：2018-11-28

申请人： Micron Technology, Inc.

发明人： Seng Kim Dalson Ye ,  Chin Hui Chong

IPC分类号： H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/13 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/11 ,  H01L25/075 ,  H01L25/07 ,  H01L25/04

摘要： A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

公开(公告)号：US10153254B2

公开(公告)日：2018-12-11

申请号：US15419913

申请日：2017-01-30

申请人： Micron Technology, Inc.

发明人： Seng Kim Dalson Ye ,  Chin Hui Chong

IPC分类号： H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L23/13 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/075

摘要： A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.