Invention Grant
- Patent Title: Method of fabricating semiconductor structure with improved critical dimension control
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Application No.: US14989802Application Date: 2016-01-07
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Publication No.: US09653345B1Publication Date: 2017-05-16
- Inventor: Shang-Nan Chou , Che-Yi Lin , En-Chiuan Liou , Yu-Ting Hung , Shin-Feng Su , Chia-Hsun Tseng
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/768 ; H01L21/027 ; H01L21/308
Abstract:
A method of fabricating a semiconductor structure for improving critical dimension control is provided in the present invention. The method includes the following steps. An inter metal dielectric (IMD) layer is formed on a semiconductor substrate, a patterned hard mask layer is formed on the IMD layer, and a first aperture is formed in the IMD layer. A first barrier layer is formed on the patterned hard mask layer and a surface of the first aperture, a first patterned resist is formed on the first barrier layer, and an etching process is performed to form a second aperture in the IMD layer by using the first patterned resist as a mask. The first patterned resist is kept from being poisoned because of the first barrier layer, and the critical dimension control of the semiconductor structure may be improved accordingly.
Information query
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