公开(公告)号：US09653345B1

公开(公告)日：2017-05-16

申请号：US14989802

申请日：2016-01-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shang-Nan Chou ,  Che-Yi Lin ,  En-Chiuan Liou ,  Yu-Ting Hung ,  Shin-Feng Su ,  Chia-Hsun Tseng

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/027 ,  H01L21/308

CPC classification number: H01L21/76802 ,  H01L21/0276 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76832

Abstract: A method of fabricating a semiconductor structure for improving critical dimension control is provided in the present invention. The method includes the following steps. An inter metal dielectric (IMD) layer is formed on a semiconductor substrate, a patterned hard mask layer is formed on the IMD layer, and a first aperture is formed in the IMD layer. A first barrier layer is formed on the patterned hard mask layer and a surface of the first aperture, a first patterned resist is formed on the first barrier layer, and an etching process is performed to form a second aperture in the IMD layer by using the first patterned resist as a mask. The first patterned resist is kept from being poisoned because of the first barrier layer, and the critical dimension control of the semiconductor structure may be improved accordingly.