- 专利标题: Approach for reducing pixel pitch using vertical transfer gates and implant isolation regions
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申请号: US14490824申请日: 2014-09-19
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公开(公告)号: US09659987B2公开(公告)日: 2017-05-23
- 发明人: Tzu-Jui Wang , Yuichiro Yamashita , Seiji Takahashi , Jen-Cheng Liu
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Eschweiler & Potashnik, LLC
- 主分类号: H01L27/146
- IPC分类号: H01L27/146
摘要:
An active pixel sensor (APS) with a vertical transfer gate and a pixel transistor (e.g., a transfer transistor, a source follower transistor, a reset transistor, or a row select transistor) electrically isolated by an implant isolation region is provided. A semiconductor substrate has a photodetector buried therein. The vertical transfer gate extends into the semiconductor substrate with a channel region in electrical communication with the photodetector. The pixel transistor is arranged over the photodetector and configured to facilitate the pixel operation (e.g., reset, signal readout, etc.). The implant isolation region is arranged in the semiconductor substrate and surrounds and electrically isolates the pixel transistor. A method for manufacturing the APS is also provided.
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