Invention Grant
- Patent Title: Selecting a low power state based on cache flush latency determination
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Application No.: US14221696Application Date: 2014-03-21
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Publication No.: US09665153B2Publication Date: 2017-05-30
- Inventor: Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F12/0815 ; G06F12/0804 ; G06F12/084 ; G06F12/0811
Abstract:
In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
Public/Granted literature
- US20150268711A1 Selecting A Low Power State Based On Cache Flush Latency Determination Public/Granted day:2015-09-24
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