公开(公告)号：US20190162782A1

公开(公告)日：2019-05-30

申请号：US15825352

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jeff Huxel ,  Wei Li ,  Sanjoy Mondal ,  Arvind Raman

IPC: G01R31/3187 ,  G01R31/319 ,  G01R31/317 ,  G06F1/32

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

公开(公告)号：US20170220099A1

公开(公告)日：2017-08-03

申请号：US15484361

申请日：2017-04-11

Applicant: Intel Corporation

Inventor： Aswin Ramachandran ,  Arvind Raman

IPC: G06F1/32 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/0724 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

公开(公告)号：US20220091652A1

公开(公告)日：2022-03-24

申请号：US17128076

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Pascal Meinerzhagen ,  Suyoung Bang ,  Abdullah Afzal ,  Karthik Subramanian ,  Muhammad Khellah ,  Arvind Raman

IPC: G06F1/324 ,  H03K19/0175 ,  G06F1/12 ,  G06F1/08 ,  G06F1/3296

Abstract: Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).

公开(公告)号：US10198065B2

公开(公告)日：2019-02-05

申请号：US15494625

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US20170228014A1

公开(公告)日：2017-08-10

申请号：US15494625

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0808

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/314 ,  G06F2212/621 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US09335813B2

公开(公告)日：2016-05-10

申请号：US13903744

申请日：2013-05-28

Applicant: Intel Corporation

Inventor： James S. Burns ,  Ashish V. Choubal ,  Arvind Raman ,  Johan G. Van De Groenendaal

IPC: G06F1/32 ,  G06F1/00 ,  G06F1/26 ,  G01R27/00 ,  G06F1/20

CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/329

Abstract: A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention, the processor uses the variation in the leakage current of the processor to reduce the maximum current dissipation or power supply current of the processor (ICCmax). By reducing the maximum current dissipation, the system cost can be reduced as a less expensive power delivery system is required in one embodiment of the invention.

Abstract translation: 一种用于处理器的漏电流和动态电源电流的动态或运行时重新分配的方法和系统。 在本发明的一个实施例中，处理器使用处理器的漏电流的变化来减小处理器的最大电流消耗或电源电流（ICCmax）。 通过减少最大电流消耗，可以减少系统成本，因为在本发明的一个实施例中需要较便宜的电力输送系统。

公开(公告)号：US10962596B2

公开(公告)日：2021-03-30

申请号：US16839238

申请日：2020-04-03

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jeff Huxel ,  Wei Li ,  Sanjoy Mondal ,  Arvind Raman

IPC: G06F11/00 ,  G01R31/3187 ,  G06F1/3203 ,  G01R31/317 ,  G01R31/319 ,  G06F1/3234 ,  G06F11/34 ,  G06F11/07 ,  G06F11/273 ,  G06F11/22 ,  G06F11/263

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

公开(公告)号：US10374584B1

公开(公告)日：2019-08-06

申请号：US15916130

申请日：2018-03-08

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Muhammad Khellah ,  Arvind Raman ,  Feroze Merchant ,  Ashish Choubal

IPC: H03K3/037 ,  G01R31/3185

Abstract: An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.

公开(公告)号：US10261572B2

公开(公告)日：2019-04-16

申请号：US15484361

申请日：2017-04-11

Applicant: Intel Corporation

Inventor： Aswin Ramachandran ,  Arvind Raman

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3228 ,  G06F9/4401 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/07

Abstract: Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

公开(公告)号：US20200300911A1

公开(公告)日：2020-09-24

申请号：US16839238

申请日：2020-04-03

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jeff Huxel ,  Wei Li ,  Sanjoy Mondal ,  Arvind Raman

IPC: G01R31/3187 ,  G06F1/3203 ,  G01R31/317 ,  G01R31/319 ,  G06F1/3234 ,  G06F11/00 ,  G06F11/34 ,  G06F11/07

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.