公开(公告)号：US10963038B2

公开(公告)日：2021-03-30

申请号：US16252816

申请日：2019-01-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3203 ,  G06F1/3296 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F1/324 ,  G06F1/3234 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/12

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US20190155370A1

公开(公告)日：2019-05-23

申请号：US16252816

申请日：2019-01-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/3287 ,  G06F1/3296 ,  G06F1/3203 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/0808 ,  G06F1/324 ,  G06F1/3234 ,  G06F12/0815

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US09665153B2

公开(公告)日：2017-05-30

申请号：US14221696

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/314 ,  G06F2212/621 ,  G06F2212/69 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US10198065B2

公开(公告)日：2019-02-05

申请号：US15494625

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

公开(公告)号：US20170228014A1

公开(公告)日：2017-08-10

申请号：US15494625

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Sundar Ramani ,  Arvind Raman ,  Arvind Mandhani ,  Ashish V. Choubal ,  Kalyan Muthukumar ,  Ajaya V. Durg ,  Samudyatha Chakki

IPC: G06F1/32 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0808

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/314 ,  G06F2212/621 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.