- Patent Title: Apparatus and method to optimize STT-MRAM size and write error rate
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Application No.: US14913676Application Date: 2013-09-27
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Publication No.: US09711215B2Publication Date: 2017-07-18
- Inventor: Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2013/062421 WO 20130927
- International Announcement: WO2015/047337 WO 20150402
- Main IPC: G11C11/16
- IPC: G11C11/16 ; G11C5/02 ; G11C5/06 ; G11C5/08 ; G11C13/00 ; G11C11/56

Abstract:
Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.
Public/Granted literature
- US20160203865A1 APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE Public/Granted day:2016-07-14
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