Invention Grant
- Patent Title: Apparatuses and methods to perform post package trim
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Application No.: US14539331Application Date: 2014-11-12
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Publication No.: US09741403B2Publication Date: 2017-08-22
- Inventor: Alan J. Wilson , Jeffrey P. Wright
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C5/00
- IPC: G11C5/00 ; G11C7/20 ; G11C11/4072 ; G11C16/20 ; G11C29/02 ; G11C11/4093 ; G11C11/4076 ; G11C16/06 ; G11C7/22 ; G11C17/18

Abstract:
Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.
Public/Granted literature
- US20160133310A1 APPARATUSES AND METHODS TO PERFORM POST PACKAGE TRIM Public/Granted day:2016-05-12
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