公开(公告)号：US11610613B2

公开(公告)日：2023-03-21

申请号：US17212708

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22 ,  G11C11/4093

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US11381432B2

公开(公告)日：2022-07-05

申请号：US17123990

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: H04L27/04 ,  G06F13/38 ,  H04L27/06 ,  H04L27/02 ,  H04L25/49 ,  G06F13/16 ,  G11C5/06 ,  G11C7/10

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

公开(公告)号：US20200327057A1

公开(公告)日：2020-10-15

申请号：US16912434

申请日：2020-06-25

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F12/0806 ,  H04L5/00

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

公开(公告)号：US20190148314A1

公开(公告)日：2019-05-16

申请号：US16138003

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Kevin G. Duesman ,  Jeffrey P. Wright ,  Warren L. Boyer

IPC: H01L23/60 ,  H01L23/538 ,  H01L23/00 ,  H01L25/04

CPC classification number: H01L23/60 ,  G11C5/02 ,  G11C5/025 ,  H01L23/538 ,  H01L24/02 ,  H01L24/10 ,  H01L24/95 ,  H01L25/043 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.

公开(公告)号：US10002659B2

公开(公告)日：2018-06-19

申请号：US15265677

申请日：2016-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

IPC: G06F13/10 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

公开(公告)号：US20170323675A1

公开(公告)日：2017-11-09

申请号：US15656084

申请日：2017-07-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William F. Jones ,  Jeffrey P. Wright

IPC: G11C8/10 ,  G11C29/00 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C8/10 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4087 ,  G11C17/16 ,  G11C17/18 ,  G11C29/783 ,  G11C2211/4068

Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

公开(公告)号：US09378791B2

公开(公告)日：2016-06-28

申请号：US14800512

申请日：2015-07-15

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P. Wright

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/00

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

公开(公告)号：US09159397B2

公开(公告)日：2015-10-13

申请号：US13693865

申请日：2012-12-04

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Jeffrey P. Wright

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40611

Abstract: Apparatuses and methods for memory refreshing memory cells is described. An example method includes receiving a self refresh command at a memory. The method further includes refreshing the memory at a first refresh rate after receiving the self refresh command. The method further includes refreshing the memory at a second refresh rate in response to a determination that each memory cell of the memory has been refreshed at the first refresh rate. The first refresh rate is greater than a second refresh rate.

Abstract translation: 描述了用于存储器刷新存储器单元的装置和方法。 一种示例性方法包括在存储器处接收自刷新命令。 该方法还包括在接收到自刷新命令之后以第一刷新速率刷新存储器。 该方法还包括响应于确定存储器的每个存储器单元已经以第一刷新率刷新的第二刷新率刷新存储器。 第一次刷新率大于第二次刷新率。

公开(公告)号：US20240369632A1

公开(公告)日：2024-11-07

申请号：US18772690

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Kenneth M. Curewitz ,  Jaime Cummins ,  John D. Porter ,  Bryce D. Cook ,  Jeffrey P. Wright

IPC: G01R31/319 ,  G01R31/3185

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.

公开(公告)号：US12072381B2

公开(公告)日：2024-08-27

申请号：US18047386

申请日：2022-10-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Jaime Cummins ,  John D. Porter ,  Bryce D. Cook ,  Jeffrey P. Wright

IPC: G01R31/319 ,  G01R31/3185

CPC classification number: G01R31/31907 ,  G01R31/318594 ,  G01R31/318597

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.