发明授权
- 专利标题： Damage reduction method and apparatus for destructive testing of power semiconductors
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申请号： US13560233申请日： 2012-07-27
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公开(公告)号： US09759763B2公开(公告)日： 2017-09-12
- 发明人: Rodney E. Schwartz , Steve Clauter , David Lohr , Gary Rogers , James Baggiore
- 申请人： Rodney E. Schwartz , Steve Clauter , David Lohr , Gary Rogers , James Baggiore
- 申请人地址： US AZ Temp
- 专利权人： Integrated Technology Corporation
- 当前专利权人： Integrated Technology Corporation
- 当前专利权人地址： US AZ Temp
- 代理机构： Renner, Otto, Boisselle & Sklar LLP
- 主分类号： G01R1/067
- IPC分类号： G01R1/067 ; G01R1/36 ; G01R31/12 ; G01R31/27 ; G01R31/28 ; G01R31/26 ; G01R31/02
摘要：
A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device.
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