Invention Grant
- Patent Title: Cut last self-aligned litho-etch patterning
-
Application No.: US15170090Application Date: 2016-06-01
-
Publication No.: US09761451B2Publication Date: 2017-09-12
- Inventor: Kuan-Wei Huang , Chia-Ying Lee , Ming-Chung Liang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L27/11

Abstract:
The present disclosure relates to a method of performing a semiconductor fabrication process. In some embodiments, the method is performed by forming a spacer material within openings in a first masking layer overlying a second masking layer, and forming a reverse material over a part of the spacer material. A first plurality of openings are formed within the spacer material. The first plurality of openings are separated by the reverse material. A second plurality of openings are formed within the first masking layer. The second plurality of openings are separated by the spacer material. The second masking layer is patterned according to the first plurality of openings and the second plurality of openings.
Public/Granted literature
- US20160276154A1 CUT LAST SELF-ALIGNED LITHO-ETCH PATTERNING Public/Granted day:2016-09-22
Information query
IPC分类: