公开(公告)号：US12040233B2

公开(公告)日：2024-07-16

申请号：US17329998

申请日：2021-05-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng Jhe Tsai ,  Hong-Jie Yang ,  Meng-Chun Chang ,  Hao Chiang ,  Chia-Ying Lee ,  Huan-Just Lin ,  Chuan Chang

IPC分类号： H01L21/82 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851

摘要： A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

公开(公告)号：US11901180B2

公开(公告)日：2024-02-13

申请号：US17670990

申请日：2022-02-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L21/027 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/0274 ,  H01L21/308 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/785

摘要： A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US20220172945A1

公开(公告)日：2022-06-02

申请号：US17670990

申请日：2022-02-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L21/027 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308

摘要： A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US20200234972A1

公开(公告)日：2020-07-23

申请号：US16837252

申请日：2020-04-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ying Lee ,  Jyu-Horng Shieh

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/027

摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.

公开(公告)号：US10109486B2

公开(公告)日：2018-10-23

申请号：US15633152

申请日：2017-06-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC分类号： H01L21/44 ,  H01L21/033 ,  H01L21/768 ,  H01L21/461

摘要： The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.

公开(公告)号：US20170365472A1

公开(公告)日：2017-12-21

申请号：US15696498

申请日：2017-09-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC分类号： H01L21/033 ,  H01L27/11

摘要： The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.

公开(公告)号：US08962432B2

公开(公告)日：2015-02-24

申请号：US14161986

申请日：2014-01-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ying Lee ,  Jyu-Horng Shieh

IPC分类号： H01L21/336 ,  H01L21/768

CPC分类号： H01L21/76807 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

摘要： A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.

摘要翻译： 使用镶嵌技术形成半导体器件的方法提供端对端间隔小于60nm而不短路的自对准导电线。 该方法包括使用至少一个牺牲硬掩模层来产生心轴并在心轴中形成空隙。 牺牲硬掩模层形成在有利地是绝缘材料的基材上。 在一些实施例中，另一个硬掩模层也设置在基体材料上并在心轴下方。 垫片材料沿心轴形成并填充空隙。 间隔材料用作掩模，并且执行至少一个蚀刻程序以将间隔物材料的图案转化为基底材料。 图案化的基材包括沟槽和凸起部分。 使用镶嵌技术在沟槽中形成导电特征。

公开(公告)号：US20140273433A1

公开(公告)日：2014-09-18

申请号：US13920201

申请日：2013-06-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ying Lee ,  Jyu-Horng Shieh

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/027 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76883

摘要： Self-aligned double patterning methods that can be used in back-end-of-line (BEOL) processing and other stages of integrate circuit device manufacturing. In these methods, line termini are masked prior to self-aligned double patterning. The self-aligned double patterning involves forming a mandrel, the shape of which is determined by a lithographic mask. That same lithographic mask is used prior to self-aligned double patterning to trim the mask that determines the locations of line termini. The methods provide precise positioning of the line termini mask relative to the line locations determined by self-aligned double patterning. The methods forms consistent end-of-line shapes and allow line termini to be placed more closely together than would otherwise be feasible.

摘要翻译： 自对准双重图案化方法，可用于后端行（BEOL）处理和集成电路器件制造的其他阶段。 在这些方法中，在自对准双重图案化之前掩蔽线末端。 自对准双图案包括形成心轴，其形状由光刻掩模确定。 在自对准双重图案化之前使用相同的光刻掩模来修整确定线末端位置的掩模。 该方法提供线路终端掩模相对于通过自对准双重图案化确定的线路位置的精确定位。 这些方法形成一致的行尾形状，并允许线路终端与其他情况相比更紧密地放置在一起。

公开(公告)号：US20240136183A1

公开(公告)日：2024-04-25

申请号：US18402563

申请日：2024-01-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L21/027 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/0274 ,  H01L21/308 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/785

摘要： A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US11521857B2

公开(公告)日：2022-12-06

申请号：US16163878

申请日：2018-10-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC分类号： H01L21/3105 ,  H01L21/033 ,  H01L21/768 ,  H01L27/11 ,  H01L21/461

摘要： The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer.