公开(公告)号：US20240379414A1

公开(公告)日：2024-11-14

申请号：US18782335

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Nien Su ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

公开(公告)号：US20230282488A1

公开(公告)日：2023-09-07

申请号：US18316620

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3085 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76898

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

公开(公告)号：US20210125836A1

公开(公告)日：2021-04-29

申请号：US17018705

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

公开(公告)号：US20170294311A1

公开(公告)日：2017-10-12

申请号：US15633152

申请日：2017-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC: H01L21/033 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L21/461 ,  H01L21/76816 ,  H01L27/1116

Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.

公开(公告)号：US09761451B2

公开(公告)日：2017-09-12

申请号：US15170090

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC: H01L21/033 ,  H01L27/11

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L27/11

Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. In some embodiments, the method is performed by forming a spacer material within openings in a first masking layer overlying a second masking layer, and forming a reverse material over a part of the spacer material. A first plurality of openings are formed within the spacer material. The first plurality of openings are separated by the reverse material. A second plurality of openings are formed within the first masking layer. The second plurality of openings are separated by the spacer material. The second masking layer is patterned according to the first plurality of openings and the second plurality of openings.

公开(公告)号：US12165914B2

公开(公告)日：2024-12-10

申请号：US17369497

申请日：2021-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Nien Su ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

公开(公告)号：US20240387248A1

公开(公告)日：2024-11-21

申请号：US18787890

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Yu-Yu Chen

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A patterning process that can be utilized in order to help form conductive lines within a dielectric layer of a metallization layer is provided. In an embodiment a first interfacial layer is patterned a first time, the first interfacial layer being located over a first hard mask layer over a dielectric layer, the patterning the first interfacial layer the first time forming a first opening, which is filled with a first dielectric material. The first interfacial layer is patterned a second time, the patterning the first interfacial layer the second time forming second openings in the first interfacial layer, at least one of the second openings exposing the first dielectric material. The first dielectric material is removed, and the dielectric layer is patterned a second time after the removing the first dielectric material using the first interfacial layer as a mask, the patterning the dielectric layer extending the second openings.

公开(公告)号：US11676821B2

公开(公告)日：2023-06-13

申请号：US17018705

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/3085 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76898

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

公开(公告)号：US20220148918A1

公开(公告)日：2022-05-12

申请号：US17586412

申请日：2022-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Cheng-Li Fan ,  Yu-Yu Chen

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.

公开(公告)号：US10109486B2

公开(公告)日：2018-10-23

申请号：US15633152

申请日：2017-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC: H01L21/44 ,  H01L21/033 ,  H01L21/768 ,  H01L21/461

Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.