公开(公告)号：US11676821B2

公开(公告)日：2023-06-13

申请号：US17018705

申请日：2020-09-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

IPC分类号： H01L21/308 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/3085 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76898

摘要： A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

公开(公告)号：US20220148918A1

公开(公告)日：2022-05-12

申请号：US17586412

申请日：2022-01-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Cheng-Li Fan ,  Yu-Yu Chen

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

摘要： A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.

公开(公告)号：US10109486B2

公开(公告)日：2018-10-23

申请号：US15633152

申请日：2017-06-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC分类号： H01L21/44 ,  H01L21/033 ,  H01L21/768 ,  H01L21/461

摘要： The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.

公开(公告)号：US20170365472A1

公开(公告)日：2017-12-21

申请号：US15696498

申请日：2017-09-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC分类号： H01L21/033 ,  H01L27/11

摘要： The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.

公开(公告)号：US20230282488A1

公开(公告)日：2023-09-07

申请号：US18316620

申请日：2023-05-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/3085 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76898

摘要： A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

公开(公告)号：US20210125836A1

公开(公告)日：2021-04-29

申请号：US17018705

申请日：2020-09-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

IPC分类号： H01L21/308 ,  H01L21/768 ,  H01L21/311

摘要： A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

公开(公告)号：US20170294311A1

公开(公告)日：2017-10-12

申请号：US15633152

申请日：2017-06-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC分类号： H01L21/033 ,  H01L21/461 ,  H01L21/768

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L21/461 ,  H01L21/76816 ,  H01L27/1116

摘要： The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.

公开(公告)号：US09761451B2

公开(公告)日：2017-09-12

申请号：US15170090

申请日：2016-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC分类号： H01L21/033 ,  H01L27/11

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L27/11

摘要： The present disclosure relates to a method of performing a semiconductor fabrication process. In some embodiments, the method is performed by forming a spacer material within openings in a first masking layer overlying a second masking layer, and forming a reverse material over a part of the spacer material. A first plurality of openings are formed within the spacer material. The first plurality of openings are separated by the reverse material. A second plurality of openings are formed within the first masking layer. The second plurality of openings are separated by the spacer material. The second masking layer is patterned according to the first plurality of openings and the second plurality of openings.

公开(公告)号：US12002710B2

公开(公告)日：2024-06-04

申请号：US16924200

申请日：2020-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hsin Chan ,  Jiing-Feng Yang ,  Kuan-Wei Huang ,  Meng-Shu Lin ,  Yu-Yu Chen ,  Chia-Wei Wu ,  Chang-Wen Chen ,  Wei-Hao Lin ,  Ching-Yu Chang

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528

CPC分类号： H01L21/76816 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/528

摘要： A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

公开(公告)号：US20220384201A1

公开(公告)日：2022-12-01

申请号：US17883930

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

IPC分类号： H01L21/308 ,  H01L21/768 ,  H01L21/311

摘要： A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.