Invention Grant
- Patent Title: AVD hardmask for damascene patterning
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Application No.: US15332199Application Date: 2016-10-24
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Publication No.: US09780038B2Publication Date: 2017-10-03
- Inventor: Ruth A. Brain , Kevin J. Fischer , Michael A. Childs
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/532 ; H01L21/768 ; H01L23/498 ; H01L23/522 ; H01L23/528 ; H01L21/311

Abstract:
A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
Public/Granted literature
- US20170040263A1 AVD HARDMASK FOR DAMASCENE PATTERNING Public/Granted day:2017-02-09
Information query
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