公开(公告)号：US20170040263A1

公开(公告)日：2017-02-09

申请号：US15332199

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Ruth A. Brain ,  Kevin J. Fischer ,  Michael A. Childs

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

Abstract translation: 一种包括在集成电路结构的接触点上形成介电层的方法; 在所述电介质层的表面上形成包括电介质材料的硬掩模; 以及使用所述硬掩模作为图案在所述电介质层中形成至少一个通孔到所述接触点。 一种包括电路基板的装置，包括至少一个包括接触点的活性层; 所述至少一个有源层上的介电层; 包括其中具有用于互连材料的至少一个开口的电介质材料的硬掩模; 以及在硬掩模的至少一个开口中并通过介电层到接触点的互连材料。

公开(公告)号：US10229879B2

公开(公告)日：2019-03-12

申请号：US15274175

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Kevin J. Fischer ,  Christopher M. Pelto ,  Andrew W. Yeoh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

公开(公告)号：US09437545B2

公开(公告)日：2016-09-06

申请号：US14569342

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jun He ,  Kevin J. Fischer ,  Ying Zhou ,  Peter K. Moon

IPC: H01L23/52 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/76849 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

公开(公告)号：US20240071831A1

公开(公告)日：2024-02-29

申请号：US17896813

申请日：2022-08-26

Applicant: INTEL CORPORATION

Inventor： Chang Wan Han ,  Biswajeet Guha ,  Vivek Thirtha ,  William Hsu ,  Ian Yang ,  Oleg Golonzka ,  Kevin J. Fischer ,  Suman Dasgupta ,  Sameerah Desnavi ,  Deepak Sridhar

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure

公开(公告)号：US09984922B2

公开(公告)日：2018-05-29

申请号：US15254840

申请日：2016-09-01

Applicant: Intel Corporation

Inventor： Jun He ,  Kevin J. Fischer ,  Ying Zhou ,  Peter K. Moon

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/76849 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

公开(公告)号：US20170011997A1

公开(公告)日：2017-01-12

申请号：US15274175

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Kevin J. Fischer ,  Christopher M. Pelto ,  Andrew W. Yeoh

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

Abstract translation: 实施例包括半导体结构，包括：包括器件层的前端部分; 后底部分，其包括底部金属层，顶部金属层和位于底部和顶部金属层之间的中间金属层; 其中（a）顶部金属层包括与顶部金属层所在的水平面正交的第一厚度，底部金属层包括第二厚度; 并且所述中间金属层包括第三厚度; 和（b）第一厚度大于或等于第二和第三厚度之和。 本文描述了其它实施例。

公开(公告)号：US09496173B2

公开(公告)日：2016-11-15

申请号：US14137487

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Kevin J. Fischer ,  Christopher M. Pelto ,  Andrew W. Yeoh

IPC: H01L23/498 ,  H01L23/522 ,  H01L21/68 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

Abstract translation: 实施例包括半导体结构，包括：包括器件层的前端部分; 后底部分，其包括底部金属层，顶部金属层和位于底部和顶部金属层之间的中间金属层; 其中（a）顶部金属层包括与顶部金属层所在的水平面正交的第一厚度，底部金属层包括第二厚度; 并且所述中间金属层包括第三厚度; 和（b）第一厚度大于或等于第二和第三厚度之和。 本文描述了其它实施例。

公开(公告)号：US20220415892A1

公开(公告)日：2022-12-29

申请号：US17358073

申请日：2021-06-25

Applicant: INTEL CORPORATION

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Conor P. Puls ,  Mauro J. Kobrinsky ,  Kevin J. Fischer ,  Derchang Kau ,  Albert Fazio ,  Tahir Ghani

IPC: H01L27/105

Abstract: Integrated circuit (IC) devices with stacked two-level backend memory, and associated systems and methods, are disclosed. An example IC device includes a front end of line (FEOL) layer, including frontend transistors, and a back end of line (BEOL) layer above the FEOL layer. The BEOL layer includes a first memory layer with memory cells of a first type, and a second memory layer with memory cells of a second type. The first memory layer may be between the FEOL layer and the second memory layer, thus forming stacked backend memory. Stacked backend memory architecture may allow significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. Implementing two different types of backend memory may advantageously increase functionality and performance of backend memory.

公开(公告)号：US10593626B2

公开(公告)日：2020-03-17

申请号：US15723083

申请日：2017-10-02

Applicant: Intel Corporation

Inventor： Ruth A. Brain ,  Kevin J. Fischer ,  Michael A. Childs

IPC: H01L23/532 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

公开(公告)号：US09780038B2

公开(公告)日：2017-10-03

申请号：US15332199

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Ruth A. Brain ,  Kevin J. Fischer ,  Michael A. Childs

IPC: H01L23/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/5329 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.