Invention Grant
- Patent Title: High frequency delay lock loop systems
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Application No.: US15235290Application Date: 2016-08-12
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Publication No.: US09806722B2Publication Date: 2017-10-31
- Inventor: Guojun Ren , James Gorecki , Karthik S. Gopalakrishnan
- Applicant: INPHI CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INPHI CORPORATION
- Current Assignee: INPHI CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Ogawa P.C.
- Agent Richard T. Ogawa
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/08 ; H03L7/085 ; H03L7/081

Abstract:
The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
Public/Granted literature
- US20170033799A1 HIGH FREQUENCY DELAY LOCK LOOP SYSTEMS Public/Granted day:2017-02-02
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