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公开(公告)号：US10014836B1
公开(公告)日：2018-07-03
申请号：US15418487
申请日：2017-01-27
Applicant: INPHI CORPORATION
Inventor： James Gorecki
CPC classification number: H03G1/007 , H03F1/0205 , H03F1/56 , H03F3/45197 , H03F2203/45492 , H03G3/001
Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.
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Patent Agency Ranking
公开(公告)号：US09438255B1
公开(公告)日：2016-09-06
申请号：US14815694
申请日：2015-07-31
Applicant: Inphi Corporation
Inventor： Guojun Ren , James Gorecki , Karthik S. Gopalakrishnan
CPC classification number: H03L7/0807 , H03L7/0805 , H03L7/0812 , H03L7/085
Abstract: The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
Abstract translation: 本发明涉及信号处理系统和电路。 根据各种实施例，DLL系统包括延迟线，其提供与不同时钟相位相关联的多个输出信号。 可以使用一对偏置电压来调整延迟线。 相位检测器系统使用来自延迟线的多个输出信号产生偏置电压。 多个输出信号包括与第一阶段，最后阶段和两个相邻阶段相关联的信号。 还有其它实施例。
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公开(公告)号：US10411666B2
公开(公告)日：2019-09-10
申请号：US15995008
申请日：2018-05-31
Applicant: INPHI CORPORATION
Inventor： James Gorecki
Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.
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公开(公告)号：US09866231B2
公开(公告)日：2018-01-09
申请号：US15426506
申请日：2017-02-07
Applicant: INPHI CORPORATION
Inventor： Michael Le , James Gorecki , Jamal Riani , Jorge Pernillo , Amber Tan , Karthik Gopalakrishnan , Belal Helal , Chang-Feng Loi , Irene Quek , Guojun Ren
CPC classification number: H03M1/38 , H03M1/0604 , H03M1/1038 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/468 , H04L25/03012 , H04L25/03019 , H04L25/03878
Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
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公开(公告)号：US09602116B1
公开(公告)日：2017-03-21
申请号：US14990309
申请日：2016-01-07
Applicant: INPHI CORPORATION
Inventor： Michael Le , James Gorecki , Jamal Riani , Jorge Pernillo , Amber Tan , Karthik Gopalakrishnan , Belal Helal , Chang-Feng Loi , Irene Quek , Guojun Ren
CPC classification number: H03M1/38 , H03M1/0604 , H03M1/1038 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/468 , H04L25/03012 , H04L25/03019 , H04L25/03878
Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
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公开(公告)号：US09806722B2
公开(公告)日：2017-10-31
申请号：US15235290
申请日：2016-08-12
Applicant: INPHI CORPORATION
Inventor： Guojun Ren , James Gorecki , Karthik S. Gopalakrishnan
CPC classification number: H03L7/0807 , H03L7/0805 , H03L7/0812 , H03L7/085
Abstract: The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
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