Techniques are disclosed to control power and processing among a plurality of asymmetric cores. In one embodiment, a multi-core processor includes first and second processing cores, each including an arithmetic logic unit and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than the second processing core, wherein the first and second processing cores have different instruction sets, wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core, wherein instructions to run on the second processing core are translated to the instruction set of the second processing core by a software binary translation shell, and wherein the first and second processing cores are to concurrently execute instructions according to their own instruction sets.