Invention Grant
- Patent Title: 3D IC bump height metrology APC
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Application No.: US14798661Application Date: 2015-07-14
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Publication No.: US09859139B2Publication Date: 2018-01-02
- Inventor: Nai-Han Cheng , Chi-Ming Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/67
- IPC: H01L21/67 ; G01B11/16 ; G01B11/14 ; G01B11/24 ; H01L21/66 ; H01L23/00 ; H01L21/768 ; H01L25/00 ; H01L25/065

Abstract:
The present disclosure relates to a method of bump metrology that relies upon advanced process control (APC) to provide substrate warpage parameters describing a warpage of a substrate to a bump metrology module to improve focus of the bump metrology module. In some embodiments, the method measures one or more substrate warpage parameters of a semiconductor substrate. An initial focal height of a lens of a bump metrology module is calculated based upon the measured substrate warpage parameters. The lens of the bump metrology module is then placed at the initial focal height, and height and critical dimensions of a plurality of bumps on the semiconductor substrate are subsequently measured using the lens. By providing the substrate warpage parameters to the bump metrology module, the bump metrology module can use real-time process control to account for wafer warpage, thereby improving throughput and yield.
Public/Granted literature
- US20170018445A1 3D IC BUMP HEIGHT METROLOGY APC Public/Granted day:2017-01-19
Information query
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