Invention Grant
- Patent Title: Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
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Application No.: US15412598Application Date: 2017-01-23
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Publication No.: US09905476B2Publication Date: 2018-02-27
- Inventor: Ruqiang Bao , Siddarth A. Krishnan , Unoh Kwon , Keith Kwong Hon Wong
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L21/3213 ; H01L29/49 ; H01L29/51 ; H01L29/66 ; H01L27/11 ; H01L29/43 ; H01L21/8234 ; H01L21/28

Abstract:
Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.
Public/Granted literature
- US20170133278A1 ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs Public/Granted day:2017-05-11
Information query
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