Invention Grant
- Patent Title: Techniques to perform forward error correction for an electrical backplane
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Application No.: US15360005Application Date: 2016-11-23
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Publication No.: US09912442B2Publication Date: 2018-03-06
- Inventor: Ilango S. Ganga , Luke Chang , Andrey Belogolovy , Andrei Ovchinnikov
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F11/00
- IPC: G06F11/00 ; H04L1/00 ; G06F11/10 ; H03M13/00

Abstract:
Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.
Public/Granted literature
- US20170104554A1 TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE Public/Granted day:2017-04-13
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